Processor Bus Fundamentals for SoC Design

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Abstract
Processor bus design and implementation are critical elements of SoC designs. Busses play a central role, both internal to the chip, where a bus might connect the CPU to an SoC's peripheral controllers, and external to the chip, where busses connect a device to a variety of external peripherals. This paper, which complements the PMC-Sierra webinar, "Processor Bus Fundamentals", discusses the importance of processor bus standards. It introduces key characteristics of processor busses, describes their evolution, and provides a review of three important public bus standards PCI Express, HyperTransport, and RapidIO as well as an overview of internal bus types. It also discusses design and verification issues critical for SoC design.

About PMC
PMC-Sierra™ is a leading provider of high speed broadband communications and storage semiconductors and MIPS-Powered™ processors for Enterprise, Access, Metro Optical Transport, Storage Area Networking and Wireless network equipment. The company offers worldwide technical and sales support, including a network of offices throughout North America, Europe and Asia. The company is publicly traded on the NASDAQ Stock Market under the PMCS symbol and is included in the S&P 500 Index.

About the Author
Brian Holden is a Principal Engineer in the Microprocessor Products Division at PMC-Sierra, who is involve in the development and standardization of processor busses. Mr. Holden is currently the Technical Chair and Vice President of the HyperTransport Consortium and serves on the board of the Network Processing Forum. He has contributed to about 20 standards efforts at six different standards bodies. Mr. Holden is the author of more than 40 technical papers, currently holds 17 U.S. patents, and was involved in the invention of CRC-based framing, which is used in many communications protocols.

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