Evolving Efficient Interconnects for High Density LIUs

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Abstract
T1/E1 Mapper/Multiplexer devices have traditionally been connected to the T1/E1 lines via clock and data interfaces. These interfaces have been simple, efficient and easy to route on a circuit board. More recently, LIU densities have increased from singles and doubles to quads, octals and beyond following a simple doubling approach. The density progression of Multiplexer/Mapper bundles has had to follow multiples of 21 or 28 ports for PDH, SONET and SDH networks.
Recent SONET/SDH Mapper and Multiplexer integration has enabled 84/63 port mappers and 3 x M13 multiplexers in a single package. This paper will illustrate the potential problems at the Mapper-LIU interface when using a clock and data interface and the system cost advantages possible with a higher speed, lower pin count alternative.

About PMC
PMC-Sierra™ is a leading provider of high speed broadband communications and storage semiconductors and MIPS-Powered™ processors for Enterprise, Access, Metro Optical Transport, Storage Area Networking and Wireless network equipment. The company offers worldwide technical and sales support, including a network of offices throughout North America, Europe and Asia. The company is publicly traded on the NASDAQ Stock Market under the PMCS symbol and is included in the S&P 500 Index.

About the Author
Gordon Oliver is a Senior Product Marketing Manager in the Service Provider Division and is responsible for SONET/SDH PDH interworking solutions, including the TEMAP/OCTLIU (T1/E1 Transport, Test Access and Transmultiplexer) product families.

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