A Guide to Processor Bus Fundamentals

Access to the webinar requires registration on PMC-Sierra's website and approval to view this webinar.

What to Expect

This webinar will:

• provide an overview of processor bus technology
• introduce the general aspects of a processor bus, which include packetization, split transactions, tokenizaton, ordering rules, error handling, configuration and maintenance
• introduce throughput, latency and concurrency considerations
• compare processor busses with classical packet oriented busses and
• describe some hybrid bus features

Specific bus types including common older standards such as ISA, EISA, PCI and PCI-X, and newer standards such as HyperTransport, PCI Express and RIO will be discussed. Example implementations will be presented to better illustrate the form and function of the newer buses.

About the Presenter

Brian Holden is a Principal Engineer in the Microprocessor Products Division at PMC-Sierra, who involves in the development and standardization of processor busses.

Mr. Holden is currently the Technical Chair of the HyperTransport Consortium and serves on the board of the Network Processing Forum. He has contributed to about 20 standards efforts at six different standards bodies. Mr. Holden is the author of more than 40 technical papers, currently holds 17 U.S. patents and was involved in the invention of CRC-based framing, which is used in many communications protocols.

Who Should Attend

• Hardware, system or integration engineers who need to evaluate processor bus types or implementations
• Engineers looking for an introduction to processor bus basics

Can't Attend the Live Event?

A recording of the broadcast, the presentation slides and a transcript will be available for download on-demand.

Webinar Requirements

• Computer with:
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