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RM7965A ™
Enhanced 1-GHz 64-Bit Microprocessor with Integrated L2 Cache and EJTAG
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Features
PRODUCT OVERVIEW
The RM7965A is a high-performance 64-bit microprocessor with
features including a seven-stage dual-issue pipeline, tightly coupled
L1 and L2 caches, and sophisticated branch prediction for
maintaining pipeline efficiency. A 200 MHz 64-bit multiplexed system address and data bus (SysAD)
enables a high-bandwidth I/O interface to a variety of system
controllers providing connectivity to a wide range of networking
peripherals. The RM7965A also contains a vectored and prioritized
interrupt controller for versatile interrupt configurations. On-chip EJTAG debug modules ensure smooth and easy debugging for
both hardware and software by allowing single-step and state examination.
The inclusion of a pipeline-rate branch instruction trace buffer
facilitates debugging under operating conditions. BENEFITS
- High-performance MIPS-Powered processor
- High-bandwidth I/O interface
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- On-chip debug support
- Extensive third-party software and debug support via the MIPS
ecosystem
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- CPU core with MIPS64-compatible Instruction Set Architecture that
features:
- 900 MHz to 1 GHz operation
- >2100 Dhrystone 2.1 MIPS at 1 GHz
- Dual-issue superscalar 7-stage pipeline
- 16-KB, 4-way set associative L1 Instruction cache
- 16-KB, 4-way set associative L1 Data cache
- 256-KB, 4-way set associative L2 cache with industry best 5-
cycle access latency
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- Error Checking and Correcting (ECC) on L2 cache
- Fast Packet Cache to assist processing of packet data
- 8K-entry branch prediction table
- Fully associative 64-entry TLB with dual pages
- High performance Floating Point unit (IEEE 754)
- Fixed-point DSP instructions such as Multiply/Add,
Multiply/Subtract, and 3 Operand Multiply
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- High-performance system interface:
- Multiple outstanding reads with out of order return
- 1600 MB/s peak throughput
- 200 MHz maximum frequency using HSTL signaling on the SysAD
bus
- Multiplexed address/data bus (SysAD) supports 1.5 V, 2.5 V, and
3.3 V I/O logic
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- Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8,
8.5, 9, 10, 11, 12, 13, 14, 15, 16, 17
- Integrated on-chip EJTAG controller
- 64-entry dynamic Trace Buffer for use in real-time trace and debug
- Two 32-bit virtually addressed Watch registers
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- Integrated performance counters:
- Contains 2 independent 32-bit counters
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- Counts over 30 processor events including mispredicted
branches
- Enables full characterization and analysis of application software
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- 256-pin CSBGA package (27x27 mm)
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Applications
- Voice Gateways
- Multiservice Access Platforms
- DSLAMs/Access Concentrators
- Remote Access Switches
- Web Switches
- Layer 3 Switches
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- Backbone Switches/Routers
- RAIDs
- Set Top Boxes
- Networked Printers
- Cellular Base Stations
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