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RM5231A
64-bit MIPS RISC Microprocessor with 32-bit System Bus

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Version Issue Date

Product Brief

PDFRM5231A/5261A 64-Bit MIPS RISC Microprocessor with 32/64-bit System Bus Short Form Data Sheet [52 kB] PMC-2010740 2  2003-02-27 

Data Sheet

Locked Document, Log In RequiredPDFRM5231A (TM) Microprocessor with 32-Bit System Bus Data Sheet [428 KB] PMC-2002174 4  2004-02-17 

Application Note

Locked Document, Log In RequiredPDFStand-by Mode for the RM52xx Family - Application Note [115 KB] PMC-2031503 2  2005-03-29 
Locked Document, Log In RequiredPDFMIPS TLB Operations - Application Note [149 KB] PMC-2031515 2  2004-08-12 
Locked Document, Log In RequiredPDFRM52x1 Cache Aliasing with 4 KB Pages Application Note [312 KB] PMC-2021685 1  2003-02-11 
Locked Document, Log In RequiredPDFKnowledge Base Items for the RM5231A MIPS RISC Microprocessor [839 kB] PMC-2020420   2002-08-22 

Errata

Locked Document, Log In RequiredPDFRM52x1 Family of Microprocessor Devices Errata [197 KB] PMC-2002299 2  2003-09-15 

Software Documentation

Locked Document, Log In RequiredPDFThin Client SDK Alpha 0.3.0 Firmware Release Notes - PDF Only [175 KB] 1  2005-08-19 
Locked Document, Log In RequiredPDFThin Client SDK Firmware Release Notes Alpha 03.03 [38.97 MB] PMC-2050456 2  2005-08-18 
Locked Document, Log In RequiredPDFMIPS IV Instruction Set [1.01 MB] PMC-2010953 3  2001-05-02 
Locked Document, Log In RequiredPDFRM5200 (TM) Family User Manual [3.54 MB] PMC-2002300 1  2001-05-09 

Models

Locked Document, Log In RequiredPDFRM5231A [34 kB] 2.01  2001-06-26 

BSDL Files

Text / Binary FileBSDL file for RM5231A PMC-9991002 1  2001-03-29 

Features

  • Dual-Issue 64-bit superscalar architecture:
    • High-performance 64-bit integer unit.
    • High-throughput fully pipelined 64-bit floating point unit (IEEE 754).
  • High performance SysAD interface:
    • 32-bit or 64-bit multiplexed system address/data bus for optimum price/performance.
    • Available with 32-bit or 64-bit external bus interface
    • Supports fractional clock ratios.
    • IEEE 1149.1 JTAG boundary scan.
  • Integrated primary caches:
    • 32 KB instruction - 2-way set associative.
    • 32 KB data - 2-way set associative.
    • Virtually indexed, physically tagged.
    • Write-back and write-through on per-page basis.
    • Pipeline restart on first double word for data cache misses.
  • 64-bit MIPS instruction set architecture:
    • Floating point multiply-add instruction increases performance in signal processing and graphics applications.
    • Conditional moves to reduce branch frequency.
    • Index address modes (register + register).
  • Integrated memory management:
    • Fully associative joint TLB (shared by I and D transistors).
    • 48 dual entries map 96 pages.
    • Variable page size (4 KB to 16 MB).
  • Embedded application enhancements:
    • Specialized DSP integer Multiply-Accumulate instructions (MAD/MADU) and 3 operand Multiply instruction (MUL).
    • Instruction and Data cache locking by set.
    • Optional dedicated exception vector for interrupts.

PACKAGING

  • QFP and ExposedPad package options.
  • RM5231A is pin compatible with RM7035C ExposedPad package, 20 x 20 mm.
  • RM5261A is pin compatible with RM7065C ExposedPad package, 24 x 24 mm.
  • Lead-free (Pb-free) option available.

Applications

  • DSLAMs/Access Concentrators
  • Remote Access Switches
  • Branch Office Routers
  • RAIDs
  • HDTV
  • PVR/DVR
  • Firewalls
  • Set Top Boxes
  • Networked Printers
  • Cellular Base Stations
 
 
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