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PM8611 SBSLITE SBI Bus Serializer / STS-12 Time Slot Interchange
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Symbols/Footprints
Features
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Monolithic integrated circuit that implements conversion between a byte-serial 77.76 MHz SBI336 bus and a redundant 777.6 Mbit/s bit-serial 8B/10B-based SBI336S bus.
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SBI converter and TDM time slot interchange.
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Byte wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
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Byte wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter.
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DS0, NxDS0, T1, E1, VT1.5, VT2, DS3 and E3 and STS-1 granular SBI336 to serial SBI336S time slot interchange.
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VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch. Requires J1 byte alignment.
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With the Narrowband Switch Element, PM8620 NSE 20G, the SBSLITE can be used to implement a switch fabric scaleable to 20 Gbit/s.
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With the Narrowband Switch Element, PM8621 NSE 8G, the SBSLITE can be used to implement a switch fabric scaleable to 8 Gbit/s.
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Integrates two independent DS0 granularity Time Slot Interchange Switches (full duplex).
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Nominal latency through the SBSLITE in DS0 mode is 125 µS. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multiframes (6 ms) or two E1 multiframes (4 ms).
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In TelecomBus mode or SBI mode without DS0 level switching nominal latency through the SBSLITE is <16 µS.
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The Time Slot Interchange Switch permits any receive or incoming byte from an input tributary to be mapped to any outgoing or transmit byte, respectively, on the associated output tributary.
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Supports working and protect serial SBI336S and TelecomBus links to support a redundant switch fabric architecture.
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Encodes and decodes byte wide SBI bus and SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.
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Encodes data from the Incoming SBI bus or TelecomBus stream to working and protect 777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
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Decodes data from working and protect 777.6 MHz LVDS serial links with 8B/10B-based encoding to the Outgoing SBI bus or TelecomBus stream.
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In SBI mode, switches Channel Associated Signaling bits, CAS, with all DS0 data.
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Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.
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Provides optional PRBS generation for each LVDS serial data link for off-line link verification. PRBS can be processed with minimum STS-1 granularity.
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Provides hardware and software control to coordinate the connection mapping of the local device, peer SBSLITE devices and companion NSE switch devices.
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Can communicate with PMC's NSE switch devices over an in-band communications channel in the LVDS links. This channel includes mechanisms for central switch fabric control and configuration.
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Derives all internal timing from a single 77.76 MHz system clock and a system frame pulse.
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Supports two sets of switch settings and a controlled method of changing settings on STS-12 frame boundaries.
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Supports an IEEE P1149.1 JTAG test port.
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Provides a 16-bit microprocessor bus interface for configuration, control and status monitoring.
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1.8 V / 3.3 V 0.18 µm CMOS technology.
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160-ball 15x15 mm PBGA.
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-40 °C to +85 °C Industrial Temperature Operation.
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Applications
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T1/E1 SONET/SDH Cross-connects and Add-Drop Multiplexers.
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OC-48 Multiservice Access Multiplexers.
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Channelized OC-12/OC-48 Any Service Any Port Switches.
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Serial backplane board interconnect and Shelf-to-Shelf cabled serial interconnect.
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Voice Gateways.
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