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PM8389 SMC-L
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Features
GENERAL
The PM8389 SMC-L is a highly integrated MIPS-based processor with a set of storage system peripherals: internal memory, Two-wire Interface(TWI), Universal Asynchronous Receiver/Transmitter (UART), General Purpose I/O (GPIO), Fan Control Ports, and expansion ports for additional memory and I/O expansion. The device is optimized for storage system applications. A complete suite of firmware development tools and application programming interfaces are available to enable quick development of SCSI Enclosure Services (SES) or custom enclosure management applications. INTEGRATED PROCESSOR FEATURES
- MIPS-based™ instruction set including 16e compressed instruction set for minimizing code space size.
- 53.125 Mhz to DC operation.
- 32-bit architecture with 5 Stagepipeline.
- Thirty-two 32-bit General Purpose Registers (GPR).
- Fixed mapping translation table.
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- Extra set of shadow GPRs for improved interrupt processing latency.
- Separate 16 KB 4-way set associative instruction and data caches to support execution out of external slow memory.
- EJTAG debug interface supports single stepping, on-chip memory access, instruction and data
breakpoints.
- 64 KB on-chip scratch RAM for local code and data storage.
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LOCAL BUS INTERFACE FEATURES
- Supports external I/O devices, RAM and Flash Memory.
- 4 programmable chip selects.
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- 8/16-bit data bus with 21-bit address space for a total of 2 MB per chip select.
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SERIAL INTERFACE FEATURES
- 4 multi-master two wire interfaces.
- 2 Universal Asynchronous Receiver Transmitter (UART) interfaces.
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- 4 Fan PWM/Tachometer interfaces.
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GENERAL PURPOSE INPUT/OUTPUT (GPIO)
- Total of 53 individually programmable I/O pins (25 dedicated, 28 shared function).
- Each I/O may operate as an input, push/pull output or open-drain output.
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- Programmable LED flash patterns.
- Configurable LED activity pattern based on external activity trigger.
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TIMER AND INTERRUPT FEATURES
- Watchdog timer which resets processor upon timeout.
- 6 general purpose 32-bit timers for generating hardware timed events and interrupts.
- 4 external maskable, edge or level sensitive interrupt pins.
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- 20 internal maskable interrupt signals for UART, TWI, GPIO, and Timer generated interrupts.
- Two 32-bit counters for generating patterns on select GPIOs.
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FIRMWARE DEVELOPMENT KIT
- SES API for utilizing SES pages transported via TWI between expander and SMC-L.
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- Peripheral Drivers: TWI, UART, GPIO,LED.
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Physical
- Built in 0.18 µm (1.8 V Core and 3.3 V I/O supply) CMOS technology.
- GPIOs are 5 V tolerant.
- Packaged in a 15 mm x 15 mm 196-pin CABGA.
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- 598mW typical operating power at
106MHz.
- 465mW typical operating power at
80MHz.
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Applications
- FC/SAS/SATA Storage Array
- Server Storage
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