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PM8385 QuadPHY RT
4 Channel Gigabit Ethernet and 1 & 2 Gbit/s Fibre Channel Retimer

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Version Issue Date

Product Brief

PDFQuadPHY RT 4-Port 1.0625/2.125 Gbit/s Fibre Channel and Gigabit Ethernet Retimer Short Form Data Sheet [106 KB] PMC-2030741 2003-12-19 

Data Sheet

PDFQuadPHY RT ASSP Standard Product Overview [379 KB] PMC-2031142 2003-11-27 
PDFQuadPHY RT ASSP Standard Product Data Sheet [871 KB] PMC-2031860 2003-12-08 

Errata

PDFPM8385 QuadPHY RT Revision A Device Errata [124 KB] PMC-2032005 2003-12-05 

Technical Overview

PDFESD 10 Gigabit Ethernet Application Sheet [212 KB] PMC-2031953 2004-12-29 
PDFDigital Video Application Sheet [223 KB] PMC-2031955 2004-12-29 
PDFESD Aerospace, Industrial and Military Imaging Application Sheet [239 KB] PMC-2031957 2004-12-29 
PDFESD SERDES Quality Overview [319 KB] PMC-2031959 2004-12-29 
PDFESD Wireless Application Sheet [313 KB] PMC-2031954 2004-08-23 
PDFESD Gigabit Ethernet Application Sheet [248 KB] PMC-2031952 2004-12-29 
PDFESD AdvancedTCA ( ATCA ) Application Sheet [310 KB] PMC-2040765 2004-09-16 
PDFESD IP-Based DSLAMs and Access Concentrators Application Sheet [289 KB] PMC-2040993 2004-08-11 
Locked Document, Log In RequiredPDFPM8385 QuadPHY RT Retimer/Repeater Performance Report [2.67 MB] PMC-2040889 2004-06-08 
PDFESD SerDes Product Selector Guide [508 KB] PMC-2031951 2003-12-16 
PDFESD Performance Computing Application Sheet [265 KB] PMC-2031958 2004-12-29 
PDFESD Medical Diagnostic Imaging Application Sheet [266 KB] PMC-2031956 2004-12-29 

BSDL Files

Locked Document, Log In RequiredPDFBoundry Scan Ddesciption Language (BSDL) Source Code for PM8385 QUADPHY RT [101 KB] PMC-2032012 2004-06-22 

Features

GENERAL

  • Supports 4 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel - Physical Interface (FC-PI) or 4 Gigabit Ethernet Retimers at 1.25 Gbit/s per IEEE 802.3z.
  • Each port supports FC 1G or 2G rate detection/auto-selection.
  • Per-port receive monitoring for loss of signal, error rate, and link level violations.
  • Supports single-ended or differential 106.25 MHz reference clock REFCLK for Fibre Channel applications or 125 Mhz reference clock for Gigabit Ethernet applications.

HIGH-SPEED INTERFACE

  • High-speed outputs with selectable pre-emphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
  • Selectable receive input equalization provides robust data recovery of highly degraded input signals.
  • Minimized board footprint and improved signal integrity achieved because:
    • No external components are required to interface the high-speed signals to optics, coax, or serial backplanes using the internal AC coupling capacitors and terminating resistors.
    • Receive input termination of 100 Ω or 150 Ω differential is selectable.
    • Source output impedance of 100 Ω or 150 Ω differential is programmable.

TEST AND CONTROL

  • Digital Loss of Link (DLOLB) detect pin outputs for monitoring individual or multiple links. DLOLB can be programmed to indicate excessive 8B/10B code error rate, loss of synchronization, loss of signal, CRC32 errors, or comma density.
  • Supports optional 2-pin serial management interface using selectable Two-Wire Interface (TWI) or MDC/MDIO protocol for configuration and diagnostic access.
  • For normal mode of operation, a management interface is not required.
  • External control pins can be over-ridden by registers.
  • Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board testing purposes.

PHYSICAL

  • 0.18 µ CMOS, 1.8 V and 3.3 V supply.
  • Small 15 mm x 15 mm footprint, 196-pin CABGA with 1 mm ball pitch.
  • Ultra-low operating power of 1.3 W typical with all 4 channels active at 2.125 G.

Applications

  • Gigabit Ethernet Backplanes.
  • Gigabit Ethernet Coax Applications.
  • Fibre Channel Backplanes.
  • Fibre Channel Storage Systems.
  • Fibre Channel Retimer Applications.
  • Gigabit Ethernet Retimer Applications.
 
 
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