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PM8379 CTS 20x4G
18-port 2/4G Fibre Channel Port Bypass Controller
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Symbols/Footprints
Features
- 20 independent rate selectable 1.0625,
2.125 or 4.25 Gbit/s physical
interfaces.
- Register and software compatible to
the PM8368 PBC 18x2G, PM8369
PBC 18x4G, PM8372 PBC 4x2G and
PM8377 PBC 4x4G.
- Compliant to FC jitter specifications on
a per-port basis.
- Supports single-ended or differential
106.25 MHz reference clock.
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- Per port monitoring and diagnostics:
- LPSM Monitoring on each port.
- Disk isolation and per port serial
loopback.
- Configurable Digital Loss of Link:
analog LOS Detect, 8B/10B
disparity errors/error rate, CRC
errors/error rate, word
synchronization error/error rate, and
compliant frequency of comma
patterns detected (configurable
thresholds for each with
corresponding pin interrupts).
- Built-in self test capability with FC
Frame Generator/Comparator.
- Supports a 106.25 MHz, 40-bit (20
receive + 20 transmit) DDR parallel
interface that acts as a 21st port. This
flexible interface enables external
functions such as enclosure
management or other user-proprietary
functions to be implemented using a
low cost FPGA.
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- Integrated cut-through switching and
arbitration management enables up to
200% improvement in EDR and IOPS.
- Parallel arbitration supported with
arbitration priority and access fairness
preserved.
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- Automatic or CPU controlled
initialization of AL_PA table.
- Supports dynamic half duplex, half/full
duplex operation, LPSM transfer state,
multicast/broadcast (OPNy).
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- Independent per-channel selectable
high-speed outputs support 8 levels of
programmable pre-emphasis and 8
levels of output swing. Selectable pre-
emphasis counteracts dielectric losses
and allow maximum reach on printed
circuit boards.
- Independent per-channel selectable
high-speed inputs support 30 levels of
programmable receive equalization for
improved signal integrity.
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- Integrated 100 Ω differential
termination for signal integrity, smaller
solution footprint, and lower
component count.
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- Supports optional 2-pin serial
management interface using
selectable Two-Wire Interface (TWI)
protocol for configuration and
diagnostic access.
- Digital Loss of Link (DLOLB) detect
outputs for monitoring individual or
multiple links
- DLOLB can be
programmed to indicate excessive
8B/10B code error rate, loss of
synchronization, loss of signal, CRC32
errors, or comma density.
- External control pins can be overridden
by registers.
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- Interrupt output to flag changes in
bypass state and DLOLB error
conditions.
- Supports built-in self-test (BIST) via
internal Fibre Channel pattern
generation and checking.
- Supports internal serial loop back
modes for each port for testing and
debugging.
- Provides a standard 5-signal IEEE
1149.1 JTAG test port for boundary
scan board testing purposes.
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- 0.13 µm (1.2 V Core and 3.3 V I/O
supply) CMOS technology.
- 27 mm x 27 mm 352-pin CSBGA+.
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- Ultra-low operating power of 6.5 W
typical with all 20 channels active at
4.250 Gbit/s.
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Applications
- SBOD Storage Systems.
- MBOD Storage Systems.
- RAID Storage Systems.
- JBOD Storage Systems.
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- FC to SATA Storage Systems.
- FC-AL Nodes.
- Fibre Channel Hubs.
- 1.0625, 2.125, and 4.25 Gbit/s
Backplanes.
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PM8379 CTS 20x4G 20-Port 4.25 Gbit/s FC-AL Cut-Through Switch Short Form Data Sheet [74 KB] PMC-2031144 
PMC-2091539 PM8379-BI CTS 20x4G 352 CSBGA CAD Symbols and Footprints [314 KB]