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PM8375 CTS 4x4G 4-Port 4.25 Gbit/s FC-AL Cut-Through Switch and Retimer
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Features
GENERAL
- Rate selectable 1.0625, 2.125, or 4.25 Gbit/s physical interfaces.
- Pin, software and register compatible with PM8372 PBC 4x2G and PM8377 PBC 4x4G.
- Compliant to FC jitter specifications on a per-port basis.
- Supports single-ended or differential 106.25 MHz reference clock.
- Per port monitoring and diagnostics:
- LPSM Monitoring on each port.
- Disk isolation and per port serial loopback.
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Configurable Digital Loss of Link: analog LOS Detect, 8B/10B disparity errors/error rate, CRC
errors/error rate, word synchronization error/error rate, and compliant frequency of comma
patterns detected (configurable thresholds for each with corresponding pin interrupts).
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- Supports hardware-only mode with dedicated programmable pins for applications that have no CPU/MPU.
- Built-in self test capability with FC Frame Generator/Comparator.
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CUT-THROUGH SWITCHING
- Integrated cut-through switching and arbitration management enables up to 75% improvement in EDR and IOPS.
- Parallel arbitration supported with arbitration priority and access fairness preserved.
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- Automatic or CPU controlled initialization of AL_PA table.
- Supports dynamic half-duplex, half/full duplex operation, LPSM transfer state, multicast/broadcast, any login BB_credit value.
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HIGH-SPEED INTERFACE
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Independent per-channel selectable high-speed outputs support 8 levels of programmable pre-emphasis and 8
levels of output swing. Selectable pre-emphasis counteracts dielectric losses and allow maximum reach on printed
circuit boards.
- Independent per-channel selectable high-speed inputs support 30 levels of programmable receive equalization for improved signal integrity.
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- Integrated 100 Ω differential termination for improved signal integrity, smaller solution footprint, and lower component count.
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TEST AND CONTROL
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Supports optional 2-pin serial management interface using selectable Two-Wire Interface (TWI)
protocol for configuration and diagnostic access.
- For retimer mode of operation, a management interface is not required.
- External control pins can be overridden by registers.
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Digital Loss of Link (DLOLB) detect outputs for monitoring individual or multiple links. DLOLB can be
programmed to indicate excessive 8B/10B code error rate, loss of synchronization, loss of signal, CRC32
errors, or comma density.
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- Interrupt output to flag changes in bypass state and DLOLB error conditions.
- Supports built-in self-test (BIST) via internal Fibre Channel pattern generation and checking.
- Supports internal serial loop back modes for each port for testing and debugging.
- Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board testing purposes.
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PHYSICAL
- 0.13 µm (1.2 V Core and 3.3 V I/O supply) CMOS technology.
- 15 mm x 15 mm footprint, 196-pin CABGA with 1 mm ball pitch.
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Applications
- FC to SATA Storage Systems.
- 1.0625, 2.125, and 4.25 Gbit/s Backplanes.
- FC Switches
- SBOD Storage Systems.
- MBOD Storage Systems.
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- RAID Storage Systems.
- JBOD Storage Systems.
- FC-AL Nodes.
- Fibre Channel Hubs.
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