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PM8374A DualPHY 1G
2 Channel 933 Mbit/s - 1.25 Gbit/s Multi-Protocol SERDES

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Version Issue Date

Data Sheet

Locked Document, Log In RequiredPDFDualPHY 1G ASSP Telecom Standard Product Data Sheet [812 KB] PMC-2040227 2004-05-18 
PDFDualPHY 1G Standard Product Short Form Data Sheet [46 KB] PMC-2040215 2004-09-03 

Application Note

PDFPMC SERDES Introduction Sheet [272 KB] PMC-2040749 2004-05-14 
PDFOctal/Quad/DualPHY 1G Board Level Design and Debug Tips [171 KB] PMC-2030175 2004-07-12 

Errata

Locked Document, Log In RequiredPDFPM8374A DualPHY 1G Revision A Device Errata [60 KB] PMC-2041514 2004-08-31 

Features

GENERAL

  • Two 933 Mbits/s to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant Transceivers.
  • Two secondary serial channels for redundant system design.
  • Integrated clock synthesis, clock recovery, serializer/deserializer, built-in self-test, 8B/10B codec and IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
  • Rate matching via IDLE character insertion and deletion capable of compensating up to ±200 ppm of clock difference between channels.
  • Pin programmable or software configurable operation using 2-pin IEEE 802.3 MDC/MDIO serial management interface.
  • Supports pin-programmable hardware only device configuration.

SERIAL INTERFACE

  • High-speed outputs feature programmable output current to optimize drive distance and power - directly drives 50 . (100 . differential) systems.
  • Integrated 100 . differential resistive termination for a smaller solution footprint, easier layout and improved signal integrity.
  • Direct AC coupled interface to copper serial backplanes, optics and coaxial cable.
  • Low threshold receive differential input threshold.

PARALLEL INTERFACE

  • Supports GMII and TBI (Ten-bit Interface) standards.
  • Single Data Rate (SDR) parallel interface with synchronous receive clock (clock forwarding).
  • Half Rate Receive Clock Mode that supports Dual Data Rate.
  • Receive channel output clocks eliminate the need for PLLs in interface ASICs
  • 1.8 V and 2.5 V interoperable; 3.3 V tolerant.

TEST FEATURES

  • IEEE 1149.1 JTAG Boundary Scan support.
  • Built-in self-test (BIST) via internal packet generator/checker.
  • Per-channel control of serial and parallel loopbacks.
  • 8B/10B error counters.

PHYSICAL

  • Ultra-low power operation using 0.18 µm CMOS technology.
  • Thermally enhanced, 289-pin, 19 mm x 19 mm Chip Array BGA package.
  • 1.8 V core and analog power.
  • I/O voltage configurable as 2.5 V or 1.8 V.
  • Designed to operate over a wide temperature range (-40 to +85 °C) and is suited for central office and outside plant equipment.

Applications

  • High-speed serial backplanes.
  • IEEE 802.3-2000 Gigabit Ethernet dense line cards.
  • ANSI X3T11 Fibre Channel dense line cards.
  • Link Aggregation.
  • Intra-system and inter-system interconnect.
  • Chassis Extender.
 
 
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