|
|
PM8373 HEXPHY 1GR 6 Channel 933 Mbit/s - 1.25 Gbit/s Multi-Protocol SERDES with RGMII Parallel Interface
Documents
> Are you seeing all
your results?
If you are a PMC-Sierra Customer or Partner you may have permission to see additional results. Please log in to display additional results. |
Features
- Six independent 1.0625 to 1.25 Gbits/s IEEE 802.3-2000 Gigabit Ethernet and Fibre Channel Physical Interfaces (FC-PI) System Compliant
Transceivers.
- Integrated clock synthesis, clock recovery, serializer/deserializer, builtin self-test, 8B/10B codec.
- IEEE 802.3-2000 Gigabit Ethernet Physical Coding Sublayer (PCS) logic.
- Rate matching via IDLE character insertion and deletion capable of
compensating up to 200 ppm of clock difference between channels.
- Pin programmable or software configurable operation using 2-pin
IEEE 802.3 MDC/MDIO serial management interface.
|
- Supports pin-programmable hardwareonly device configuration.
- Minimal external components required.
- 1.5 V and 1.8 V RGMII/RTBI interface.
- 1.8 V and 2.5 V LVCMOS interoperable for all other digital I/O.
|
- High-speed outputs feature
programmable output current to
optimize drive distance and power -
directly drives 50 Ω (100 Ω differential)
systems.
- Integrated 100
- differential resistive
termination for a smaller solution
footprint, easier layout and improved
signal integrity.
- Direct AC coupled interface to copper
serial backplanes, optics and coaxial
cable.
|
- 5-bit Dual Data Rate Interface
compliant with RGMII/RTBI v2.0
standard.
- Receive channel output clocks
eliminate the need for PLLs in interface
ASICs.
|
- 1.5 V and 1.8 V HSTL interoperable on
RGMII/RTBI digital I/O.
|
- IEEE 1149.1 JTAG Boundary Scan
support.
- Built-in self-test (BIST) via internal
packet generator/checker.
- Per-channel control of serial and
parallel loopbacks.
- 8B/10B error counters.
|
- Ultra-low power operation using 0.18
CMOS technology.
- 196-pin, 15 mm x 15 mm CABGA
package.
- 1.8 V core and analog power.
|
- 1.5 V and 1.8 V interoperable HSTL
signals.
- 1.8 V and 2.5 V interoperable
LVCMOS Signals.
- Designed to operate over a wide
temperature range (-40 to +85 C) and
is suited for central office and outside
plant equipment.
|
Applications
- High-speed serial backplanes.
- IEEE 802.3-2000 Gigabit Ethernet
dense line cards.
- ANSI X3T11 Fibre Channel dense line
cards.
|
- Link Aggregation.
- Intra-system and inter-system
interconnect.
- Chassis Extender.
|
|