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PM8368 PBC 18x2G
18-Port FC-AL Port Bypass Controller

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Version Issue Date

Product Brief

PDFPM2383-KIT PM8368 PBC 18x2G Evaluation Kit Short Form Data Sheet [63 KB] PMC-2030253 2003-09-10 
PDFPBC-18x2G 18-Port FC-AL Port Bypass Controller Short Form Data Sheet [72 KB] PMC-2020722 2004-05-07 

Application Note

Locked Document, Log In RequiredPDFDIGITAL POWER SUPPLY BYPASS GUIDELINES [453 KB] PMC-2012008 2002-02-26 

White Papers

Locked Document, Log In RequiredPDFDesigning Multi-Gigabit Serial Backplanes with High Speed SERDES Solutions [788 kB] PMC-2021636 2002-11-29 

Technical Overview

PDFESD Performance Computing Application Sheet [265 KB] PMC-2031958 2004-12-29 

Features

GENERAL

  • Supports 18 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel - Physical Interface (FC-PI).
  • Each port independently selectable to perform a retimer, repeater or analog passthru function.
  • Non-blocking crossbar switch supports configuring ports into arbitrary sized groups into arbitrary sized zones for LUN zoning.
  • Automatic selection of repeater or analog passthru function to minimize latency and jitter when a disk is bypassed.
  • Per-port receive monitoring for loss of signal, error rate, and link level violations.
  • Supports differential PECL level REFCLK at 106.25 MHz.

HIGH SPEED INTERFACE

  • Requires no external components to interface the high-speed signals to optics, coax, or serial backplanes. This results in minimum board footprint and greatly improved signal integrity.
  • High-speed outputs with selectable pre-emphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
  • Receive input equalization for improved signal integrity.
  • Programmable output current that directly drives 50 Ω lines.

TEST AND CONTROL FEATURES

  • Compatible with optional 2-pin serial management interface using the selectable two-wire industry standard interface or MDC/MDIO protocol for configuration and diagnostic access.
  • For normal mode of operation, a microprocessor interface is not required.
  • Digital Loss of Link (DLOL) detect output for monitoring individual or multiple links. DLOL can be programmed to indicate excessive error rate, loss of synchronization, loss of signal, or excessive data run length.
  • Interrupt output to flag changes in bypass state and DLOL error conditions.
  • Supports built-in self-test (BIST) via internal Fibre Channel pattern generation and checking.
  • External control pins can be overwritten by registers.
  • Supports internal serial loopback modes for each port for testing and debugging.
  • Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board purpose.

PHYSICAL CHARACTERISTICS

  • Ultra-low operating power of 4.2 W typical with all 18 channels active at 2.125 Gbit/s.
  • 0.18 µ CMOS, 1.8 V supply.
  • Small 23 mm x 23 mm footprint, 288-pin BGA with 1 mm ball pitch.

Applications

  • FC-AL Nodes.
  • RAID Storage Systems.
  • JBOD Storage Systems.
  • MBOD Storage Systems.
  • SBOD Storage Systems.
  • Fibre Channel Hubs.
  • 1.0625/2.125 Gbit/s Backplanes.
 
 
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