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PM8356 QuadPHY® FC
4 Channel 1.0625 & 2.125 Gbit/s Fibre Channel SERDES
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Features
- Four independent 1.0625 or 2.125 Gbit/s, bi-directional, Fibre Channel transceiver to 10 bit parallel interfaces.
- Integrated serializer/de-serializer, clock recovery, clock synthesis, byte alignment.
- Standalone pin configurable or software configurable.
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- No external components required to interface the high-speed signals to optics, coax, or serial backplanes.
- Integration of passive components to minimize BOM cost.
- Simple power supply filtering requirements.
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HIGH SPEED INTERFACE
- Provides working and protect high-speed differential I/O for redundant systems.
- Independent 1G/2G rate selection for transmit and receive on a per channel basis without affecting the operation of channels not going through rate selection process.
- Selectable transmit pre-emphasis and receive equalization on a per-channel basis to allow maximum reach.
- Supports differential PECL REFCLK at 106.25 MHz.
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- Programmable output current that directly drives 50 ohms.
- Provides internal 100 ohm differential termination on transmit and receive high-speed signals for optimal signal integrity.
- Integrated AC coupling.
- Lock times less than 300 bit times.
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PARALLEL INTERFACE
- Parallel interface compatible with ANSI T11.2 FC-HSPI.
- Receive recovered clock rates of 106.25 MHz for 2.125 Gbit/s operation, and 106.25 or 53.125 MHz for 1.0625 Gbits/s operation.
- Transmit clock rates of 106.25 MHz for 2.125 Gbit/s operation, and 106.25 MHz for 1.0625 Gbit/s operation.
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Provides both source-simultaneous or source-centered transmit and receive
parallel interface timing modes to simplify ASIC abd FPGA system interface implementations
- Interoperates with 2.5 V SSTL-2 or 1.8 V LVCMOS levels.
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TEST FEATURES
- Supports optional 2-pin serial management interface using MDC/MDIO protocol for configuration and diagnostic access.
- Built in self-test (BIST) via internal packet generation and checking.
- Serial and parallel loopback modes per channel for testing and debugging.
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- Standard IEEE 1149.1 JTAG test port for boundary scan board purposes.
- An evaluation kit (PM2377-KIT) is available for the QuadPHY FC.
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PHYSICAL CHARACTERISTICS
- Ultra-low power operation at 365 mW per channel using 0.18 µ CMOS technology.
- 324 pin, 23x23 mm PBGA package with 1 mm ball pitch.
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- Designed to operate over a wide temperature range and is suited for central office equipment.
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Applications
- 1.0625 Gbit/s and 2.125 Gbit/s Fibre Channel transceivers.
- High-speed serial backplanes.
- Storage Area Networking Systems.
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- Work Station/Server Fibre Channel I/O.
- Military and Industrial applications.
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