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PM8313 D3MX
M13 or M23 Single Chip Multiplexor/Demultiplexor

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Version Issue Date

Product Brief

PDFD3MX Short Form Data Sheet [70 kB] PMC-1920522 11  2002-12-17 

Reference Design

Locked Document, Log In RequiredPDFD3MX Module of the PM4944 M13 Reference Design [1.41 MB] PMC-1951045 2  1996-11-15 

Data Sheet

Locked Document, Log In RequiredPDFD3MX Data Sheet [594 kB] PMC-1920702 5  1998-08-04 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM8313 D3MX [260 kB] PMC-2020396   2003-10-06 
Locked Document, Log In RequiredPDFInterfacing the D3MX to the SSI 78P7200 DS-3 LIU [30 kB] PMC-1950946 1  1995-09-28 

Features

    GENERAL

    • Integrates a complete M13 multiplexer/demultiplexer in a single monolithic device.
    • Integral framer supports the M23 or C-bit parity DS3 formats with path maintenance data link processing and bit oriented code support for FEAC channel termination.
    • Supports either the M12 or the G.747 formats to allow DS1 or E1 signals to be multiplexed into a DS3 signal.
    • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
    • Generates an interrupt upon detection of any of various alarms, events, or changes in status. Identification of interrupt sources, masking of interrupt sources, and acknowledgement of interrupts is provided via internal registers.
    • Application compatible with the PM4341A T1XC single chip T1 Transceiver, PM4344 TQUAD quad T1 Framer and with the PM6341 E1XC single chip E1 Transceiver.
    • Provides a generic 8 bit microprocessor interface for configuration, control, and status monitoring.
    • Low power CMOS technology.
    • Available in a high density (28 by 28mm) 208 Pin PQFP package.

    DS3 FRAMER SECTION

    • Detects/inserts DS3 AIS and Idle signal - operates correctly in the presence of 10-3 bit error ratio.
    • Extracts/inserts the X,P,M,F,C and the stuff opportunity bits and serializes for optional external processing.
    • Extracts/inserts the C-bit parity mode path maintenance data link and serializes for optional external processing.
    • Extracts/inserts the C-bit parity bit-oriented codes in the Far End Alarm and Control (FEAC) channel.
    • Detects and accumulates excessive zeros (EXZ), loss of signal (LOS), line code violations (LCV) P-bit, F-bit or M-bit errors, C-bit parity errors and far end block errors (FEBE).
    • Supports DS3 line loopback and DS3 diagnostic loopback modes to assist in fault isolation.

    M23 & M12 MULTIPLEX/DEMULTIPLEX SECTIONS

    • Supports combination of 4 DS1 bit streams or the combination of 3 E1 bit streams - per G.747 into a single M12 stream.
    • Supports per DS2 payload loopback requests via C-bits or microprocessor control.
    • Accumulates DS2 M-bit, F-bit, and G.747 framing bit/word error events.
    • Supports DS2 AIS assertion based on DS3 LOF, or under microprocessor control
    • Supports DS2 tributary AIS activation/deactivation in either direction under microprocessor control
    • Inserts/detects per DS1 payload loopback requests transmitted via C-bits.

    Applications

    • M23 or C-Bit Parity Format DS1 to DS3 Mux/Demux Equipment
    • Fractional T3 Access Equipment
    • DS2 to DS3 Mux/Demux Equipment
    • DS1 to DS3 Mux/Demux Equipment Supporting G.747 Tributary Format
     
 
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