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PM8031 Tachyon QE8e+
Quad-Channel 8 Gbps Fibre Channel Controller with Encryption at Full Line Rate

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Version Issue Date

Product Brief

Locked Document, Log In RequiredPDFPM8031 Tachyon QE8e+ Quad-Channel 8 Gbps Fibre Channel Controller with Encryption at Full Line Rate Product Brief [195 KB] PMC-2061613 2008-03-05 

Application Note

Locked Document, Log In RequiredPDFAttaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 2007-05-02 

Features

PRODUCT OVERVIEW

The PM8031 Tachyon QE8e+ device is an IEEE 1619 compliant, high-performance 4-port, 8 Gbps Fibre Channel controller. It features an 8-lane native PCI-Express Gen-II link, enabling fullduplex operation simultaneously on all ports. The Tachyon QE8e+ is capable of performing 1.6 million IOPS, making it an ideal integrated single chip solution for a variety of high-performance I/O applications.

The QE8e+ features combined 64 Gbps full duplex capabilities on its 4 FC ports. Up to 4 processors per FC link are supported, allowing systems to scale to required performance, as needed.

The 1.6M IOPS capability of the QE8e+ is compatible with the Tachyon programming model at the register level, and also with the Tachyon Software Development Kit (TSDK) API tools. It features Multi-DMA, advanced frame-handling functions, and T10 DIF provides robust CRC-based data protection.

Tachyon StorClad technology delivers unparalleled encryption performance for Fibre Channel storage products. It utilizes standards-based encryption algorithms and security practices assuring vendors of FIPS-certifiable solutions when implemented with StorClad enabled products.

The QE8e+ provides bi-directional encryption/decryption capabilities at a full 8 Gbps line rate with 400K unique Data Encryption Keys per second on each port. The Flexible key management of the QE8e+ supports 1 million Data Encryption Keys (DEK) per port and 8 Key Encryption Keys (KEK) per port. Similar to DIF, DEKs may be defined on a per I/O (SEST) or a per L/A basis.

The Tachyon QE8e+ is designed to be certifiable to the FIPS 140-2 Level 3 standard. The Data encryption uses the XTS-AES algorithm, as defined by the IEEE 1619 standard, and the NIST approved AES Key Wrap algorithm is used to secure the data keys.

Product Highlights

  • 4-port 8/4/2 Gbps Fibre Channel controller
  • Supports 10 Km distance per link at 8G link rate without external memory
  • Native PCI-Express 2.0 8-lane Gen-II 5-Gbit Host Interface
  • Multiple Outbound PCIe read requests
  • Full duplex operation for each port
  • Fibre Channel auto-speed negotiation
  • Virtualization support with H/W assisted FC Frame Steering
  • Support for up to 4 processors per FC Link
  • T10 Data Integrity Field protection (T10 DIF)
  • Multi-DMA for cache mirroring
  • SCSI BiDi command assist
  • Enhanced TRE for higher performance on small data transfers
  • CRC offload engine for enabling non-T10 DIF compliant solutions
  • ERQ/SCSI LL priority control for additional Quality of Service control
  • TWI control and presence detect for optical transceivers
  • Platform-independent software development API tools including sample code for Linux, and Windows
  • Standard and RoHS compliant packages
  • Industry-leading technical support and documentation

Data Integrity Features

  • Variable block size support: 512/520 bytes
  • I/O level T10 DIF support
  • CRC Offload Engine (COE)
  • T10 DIF per L/A (DPL)

Encryption Features

  • IEEE 1619 Draft Standard Architecture for Encrypted Shared Storage Media, XTS-AES 256-bit data-at-rest encryption
  • FIPS-140-2, Levels 1-3 certifiable
  • NIST AES Key Wrap, 8 programmable Key Encryption Keys (KEK)
  • 1M Data Encryption Keys (DEK) per port
  • 400K encrypted IOPS/port

Tachyon Expressway Architecture

  • Provides an interface from the Fibre Channel core to PCI-Express
  • Allows simultaneous operation on each of the four 8 Gbit ports
  • AER and Error ECN support
  • MSI-X
  • 2K + 32-byte T10 DIF PCIe Max TLP

Preliminary Specifications

  • Package Type: 480-pin FC PBGA, 1mm ball pitch
  • Power Dissipation: 9 Watts (Estimated)
  • Thermal Specification: 0 - 110°C, Junction Temp.
  • Voltage Margin: ±5%

Maintain Tachyon Fibre Channel Family Programming Model

  • Registers memory mapped
  • Backward compatible offsets for Fibre Channel core registers
  • Similar to the Tachyon HPFC-6600/6640 QE4 device

Standard Tachyon Fibre Channel Core Feature Set

  • Performance scalable State Machine-based architecture
  • Independent, concurrent inbound/outbound transaction processing
  • Multiple outbound context support
  • Support for SCSI initiator, target and initiator/target modes
  • Complete sequence segmentation and reassembly done in hardware
  • Up to 2048-byte frame payloads
  • Fully assisted FCP Class 2 and Class 3 support
  • Class 2 ACK0/ACK1 model assists in hardware
  • Interrupt avoidance mechanisms

Applications

  • Enterprise Storage Systems
  • Embedded subsystems
  • Disk Arrays
  • Multi-protocol Bridges/Routers
  • Intelligent Switches
  • Virtualization Devices
 
 
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