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PM8002 Tachyon SPCe
8x6G 8-Port SAS/SATA Protocol Controller

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Version Issue Date

Product Brief

Locked Document, Log In RequiredPDFPM8002 Tachyon SPCe 8x6G 8-Port SAS/SATA Protocol Controller Product Brief [189 KB] PMC-2080085 2008-02-25 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped FilePMC-2080443 PM8002A Tachyon SPC 8x6G 672 FCBGA CAD Symbols and Footprints [400 KB]12008-04-17

Features

PRODUCT OVERVIEW

The Tachyon SPCe 8x6G is a highly-integrated eight-port SAS/SATA 1.5G/3G/6G Protocol Controller optimized for fabricattached RAID storage system applications and native SAS/SATA HBA applications. This cost effective solution, which features StorClad encryption technology, significantly increases total system performance, diagnostics, scalability, and manageability.

The SPCe 8x6G provides an efficient and scalable architecture that eliminates the system performance limitations of competing SAS controller devices. It provides application-programming environments that are either compatible with currently-used Tachyon Fibre Channel controllers or that can easily be ported to address specific customer environments.

The controller provides system designers with end-to-end diagnostics and error handling mechanisms to increase system performance, availability and, most importantly, manageability. Unique end-to-end features and algorithms can be achieved from host-to-hard disk drive by using the SPCe 8x6G in combination with PMC-Sierra's market leading maxSAS family of SAS/SATA expanders, muxes, and enclosure management solutions.

Tachyon StorClad technology delivers unparalleled encryption performance for SAS/SATA storage products. It utilizes standardsbased encryption algorithms and security practices assuring vendors of FIPS-certifiable solutions when implemented with StorClad-enabled products.

The SPCe 8x6G provides bi-directional encryption/decryption capabilities with 2K unique data encryption keys cached on the device. It is designed to be certifiable to the FIPS 140-2 Level 3 standard. The data encryption uses the LRW/XTS AES algorithms, as defined by the IEEE P1619 standard, and the NIST-approved ECB/CBC/CTR/GCM AES algorithms. The AES Key Wrap or Public Key Exchange algorithms can be used to secure the data keys.

The Tachyon SPCe 8x6G also supports Random Number Generator (RNG) that is ANSI X9.31-compliant and can be used for key generation and initialization vectors (IV). Furthermore, the SPCe 8x6G can perform firmware code authentication adhering to the PKA and SHA/HMAC standards.

BENEFITS

  • Higher system performance, availability and manageability
  • End-to-end system diagnostics and error handling mechanisms from host to hard disk drive
  • Lower OEM R&D development cost and increased ROI by providing a flexible Application Programming Interface that allows system integrators the ability to control the SAS/SATA protocol, protocol management, and encryption functions at the desired level of abstraction
  • Leverages Tachyon StorClad technology

PRODUCT HIGHLIGHTS

  • 1024 SAS addresses supported for high density applications
  • Minimal host CPU dependency boosts overall system performance
  • Support for up to 4K outstanding I/Os with on chip queue and on chip contexts for I/T and I/O
  • 1024 Kbytes of on-chip shared memory enables increased throughput and IOs per second (IOPS)
  • Initiator and target mode support for host-to-host transactions and failover
  • Hardware assist support for error recovery

SAS/SATA Ports

  • SAS initiator, SAS target, or SATA HBA operation on a per-PHY basis
  • SSP, SMP, STP and direct attached SATA protocol support
  • Multiplexed 3G links over a 6G serial connection for SAS protocols
  • Each PHY simultaneously supports up to 1.2 GB/s of bidirectional bandwidth
  • Flexible wide port configuration support
  • Hot-plug and SATA NCQ support

PCI Express

  • Eight lane native PCI Express-compliant 2.5 Gbit/s (PCI Express 1.1), or 5 Gbit/s PHYs (PCI Express 2.0)
 

High-Speed I/O

  • Independent per-channel selectable high-speed outputs support multiple programmable levels of pre-emphasis and output swing
  • Independent per-channel selectable high-speed inputs support multiple programmable levels of receive equalization
  • Integrated resistive termination and receiver AC coupling
  • Automatic negotiation of link speed

Encryption

  • IEEE P1619 Draft Standard Architecture for Encrypted Shared Storage Media, LRW/XTS AES data-at-rest encryption with 128/256-bit Data Encryption Key (DEK)
  • NIST-approved ECB/CBC/CTR/GCM AES algorithms with 128/192/256 bit Data Encryption Key (DEK)
  • FIPS-140-2, Levels 1-3 certifiable
  • NIST AES Key wrap support via firmware
  • 2K Data Encryption Keys (DEK)
  • FIPS 180-2 standard for SHA-1/224/256/384/512 algorithms
  • FIPS PUB 198 Keyed-Hash Message Authentication Code (HMAC) support
  • Non-deterministic Random Number Generation
  • Public Key algorithms via firmware with hardware acceleration

T10 DIF

  • Checking, insertion and replacement of T10 Data Integrity Fields (DIF) as defined by SBC-2
 

Statistics & Performance Monitoring

  • Enhanced SAS error monitoring and fault isolation
  • SAS topology monitoring and fault determination2
  • In-band communication with PMC-Sierra's maxSAS expanders and multiplexers

Configurable Peripheral Interfaces

  • NOR interface support for Flash, ROM, EEPROM and SRAM
  • Four Multi-master Two-wire Interfaces
  • Two Industry-standard 16750 UARTs
  • One SPI
  • Two SFF-8485-compliant SGPIO ports
  • Up to 20 GPIOs depending on pin configuration

Test & Control

  • Power and reset control
 

Physical

  • 90 nm (1.0 V Core, 1.2 V Analog and 3.3 V I/O) CMOS technology
  • 27 mm x 27 mm 672-pin FCBGA
  • Ultra-low operating power of 6.5 Watts at 6 Gbit/s operation

Applications

  • External RAID Storage Systems
  • Host Bus Adapters
  • Servers
 
 
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