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PM7382 FREEDM™ 32P256
32 link, 256 HDLC channel Frame Engine and Data Link Manager

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Version Issue Date

Product Brief

PDFPM2352 FREEDM-32P672 Development Kit Short Form Data Sheet [62 KB] PMC-2002000 2000-12-21 
PDFPM7382 FREEDM-32P256 Frame Engine and Data Link Manager 32P256 Short Form Data Sheet [47 kB] PMC-2011578 2001-08-02 

Reference Design

Locked Document, Log In RequiredPDFFrame Relay Port Card Reference Design [8.74 MB] PMC-1990533 2000-12-20 
Locked Document, Log In RequiredPDFFREEDM-32P672 Development Kit Platform [151 kB] PMC-2001837 2000-12-20 
Locked Document, Log In RequiredPDFFREEDM-32P672 Development Kit Board User Manual [425 kB] PMC-2001840 2000-12-21 
Locked Document, Log In RequiredPDFDesign Document for the FREEDM-32P672 Development Kit Board [2.61 MB] PMC-2001841 2000-12-21 

Data Sheet

Locked Document, Log In RequiredPDFFREEDM 32P256 DATA SHEET [940 KB] PMC-2010333 2005-12-08 

Application Note

Locked Document, Log In RequiredPDFConfiguring SBI Compatible Devices [551 KB] PMC-2020180 2007-11-20 
Locked Document, Log In RequiredPDFKnowledge Base Items for the PM7382 FREEDM-32P256 [437 kB] PMC-2020387   2003-10-06 

Errata

Locked Document, Log In RequiredPDFFREEDM 32P256 Revision A Device Errata [426 kB] PMC-2010334 2003-06-26 
Locked Document, Log In RequiredPDFFREEDM-NG Device Driver Errata [203 kB] PMC-2020677 2002-05-14 

Software Documentation

Locked Document, Log In RequiredPDFPM738X FREEDM-NG (Frame Engine and Data Link Manager) Driver Manual [549 kB] PMC-1991045 2001-12-05 

Software

Locked Document, Log In RequiredPDFPM7380, PM7381, PM7382, PM7383, PM7384, PM7385 FREEDM-NG Device Driver [99 kB] PMC-1991680 rel 1.0  2001-12-11 

BSDL Files

Text / Binary FileBOUNDARY SCAN DESCRIPTION LANGUAGE (BSDL) SOURCE CODE FOR THE PM7382 FREEDM-32P256 DEVICE [32 kB] 2002-07-25 

Features

  • Single-chip multi-channel HDLC controller with a 66 MHz, 32-bit Peripheral Component Interconnect (PCI) 2.1 compatible bus for configuration, monitoring, and transfer of packet data.
  • An on-chip DMA controller with scatter/gather capabilities.
  • Supports up to 256 bi-directional HDLC channels assigned to a maximum of 32 channelized T1/J1/E1 links. You can program the number of time-slots assigned to an HDLC channel from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).
  • Supports up to 256 bi-directional HDLC channels assigned to a maximum of 32 MVIP digital telephony buses at 2.048 Mbit/s per link, or 8 H-MVIP buses at 8.192 Mbit/s per link.
  • Supports up to 32 bi-directional HDLC channels, each assigned to an unchannelized arbitrary-rate link, subject to a maximum aggregate link clock-rate of 64 MHz in each direction.
  • Channels assigned to links 0 to 2 support clock rates up to 52 MHz. Channels assigned to links 3 to 31 support clock rates up to 10 MHz. In the special case where no more than 3 high-speed links are used, the maximum aggregate link clock-rate is 156 MHz.
  • Links configured for channelized T1/J1/E1 or unchannelized operation support the gapped-clock method for determining time-slots, which is backwards compatible with the FREEDM 8 and FREEDM 32 devices.
  • For each channel, the HDLC receiver supports programmable flag-sequence detection, bit de-stuffing and frame-check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame-check sequences.
  • For each channel, the HDLC transmitter supports programmable flag-sequence generation, bit stuffing and frame-check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame-check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.
  • Provides 32 kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. You can configure this memory to support a variety of different channel configurations: from a single channel with 32 kbytes of buffering, to 256 channels, each with a minimum of 48 bytes of buffering.
  • Provides a standard five signal P1149.1 JTAG test-port for boundary scan board-test purposes.
  • Supports 5 Volt tolerant I/Os for non-PCI signals. Supports a 3.3 Volt PCI signaling environment.
  • 329-pin plastic ball grid-array (PBGA) package.

Applications

  • IETF PPP interfaces for routers.
  • Frame Relay interfaces for ATM or Frame Relay switches and multiplexers.
  • FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexers.
  • Internet/Intranet access equipment.
  • Packet-based DSLAM equipment.
 
 
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