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PM7343 S/UNI® IMA 16
16 Link Inverse Multiplexer for ATM
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Features
- Monolithic integrated circuit supporting 16 independent T1, E1, or unchannelized physical links via a clock/data interface.
- Compliant with the ATM Forum Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function.
- On-chip hardware implements IMA 1.1 protocol including group and link state machines.
- Performs all ICP cell processing internally with no requirement for microprocessor intervention. ICP cells are also used for diagnostic purposes.
- Supports up to 16 simultaneous IMA groups.
- Supports all IMA Group Symmetry modes: symmetric/asymmetric configuration and operation.
- Performs IMA differential delay calculation and synchronization.
- Provides differential delay tolerance up to 282 ms (for T1 links) and 226 ms (for E1 links).
- Performs ICP and stuff-cell insertion and removal.
- Supports Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) transmit ICP stuffing modes.
- Supports IMA frame lengths (M) equal to 32, 64, 128, or 256.
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- Optionally supports the IMA 1.0 method of reporting Rx cell information as defined in Appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations.
- Provides IMA layer statistic counts and alarms for support of IMA Performance and Failure Alarm Monitoring and MIB support.
- Provides per link and per group counters for statistics and performance monitoring.
- Performs cell delineation on all links.
- Performs receive cell Header Error Check (HEC) and transmit cell HEC generation.
- Optionally supports transmit and receive cell payload unscrambling.
- Provides TC layer statistics counts and alarms for MIB support.
- Implemented in low power, 0.18 micron, 1.8V CMOS technology with TTL compatible inputs and outputs.
- Provides a standard 5-pin P1149 JTAG port.
- 416-ball PBGA, 27mm x 27mm.
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INTERFACE SUPPORT
- Supports 16 individual serial links (T1 or E1 or unchannelized rates up to 2.304 Mbit/s) or 8 individual serial 8 Mbit/s unchannelized links via a 2-pin line interface.
- Supports ATM over fractional T1/E1.
- Supports independent transmit clock (ITC) and common transmit clock (CTC).
- Interfaces to a 1M x 16 SDRAM (16 Mbit/s of storage for 282 msec of T1, 226 msec of E1 differential delay tolerance) through a 16-bit SDRAM interface.
- Provides a 16-bit microprocessor bus interface for configuration and Link and Unit Management.
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- ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell interfaces at clock rates up to 52 MHz.
- Any-PHY receive slave appears as single device. The PHY-ID of each cell is identified in the in-band address.
- UTOPIA L2 receive slave appears as a 16 port multi-PHY.
- UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend or in the HEC/UDF field.
- ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell interfaces at clock rates up to 52 MHz.
- Links configured for cell delineation appear as a PHY port on the Any-PHY and UTOPIA L2 bus.
- Any-PHY and UTOPIA L2 transmit slave appear as a 16-port multi-PHY. The PHY-ID of each cell is identified in the in-band address.
- Seamlessly interconnects to PM7326 S/UNI APEX ATM/Packet Traffic Manager and Switch and PM7324 S/UNI ATLAS ATM layer devices.
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LOOPBACK AND DIAGNOSTIC FEATURES
- Supports UTOPIA L2 / Any-PHY Loopback as well as Line Side Loopback.
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- Can trace ICP cells for any group.
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SOFTWARE
- The S/UNI IMA device driver, written in ANSI C, provides a well-defined Application Programming Interface (API) and low-level utility functions for diagnostics and debugging purposes.
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- Software wrappers are used for RTOS related functions making the S/UNI IMA device driver portable to any Real Time Operating System (RTOS) and hardware environment.
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Applications
- ATM Multiservice Switches – IMA/UNI and Any Service Any Port linecards
- Digital Subscriber Loop Access Multiplexers (DSLAMs)
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- Wireless Base Station Controllers
- Wireless Base Transceiver Stations
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