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PM7328 S/UNI® ATLAS™ 1K800
ATM Layer Solution, targeted at MTU and MDU access products

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Version Issue Date

Product Brief

PDFS/UNI-ATLAS-1K800 ATM Layer Solution Short Form Data Sheet [57 kB] PMC-2010037 2001-08-08 

Reference Design

Locked Document, Log In RequiredPDFDSLAM Reference Design: System Design [1.67 MB] PMC-1990832 2000-11-10 
Locked Document, Log In RequiredPDFS/UNI-ATLAS Reference Design [5.29 MB] PMC-1980583 1999-11-16 
Locked Document, Log In RequiredPDFATM Switch Using S/UNI-ATLAS, QRT, and QSE [922 kB] PMC-1990330 1999-07-23 
Locked Document, Log In RequiredPDFDSLAM Reference Design: Core Card [9.82 MB] PMC-1990815 2000-12-15 

Data Sheet

Locked Document, Log In RequiredPDFS/UNI-ATLAS-1K800 Standard Product Data Sheet [3.82 MB] PMC-2010142 2001-06-07 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM7328 S/UNI-ATLAS-1K800 [361 kB] PMC-2020366   2004-05-20 
Locked Document, Log In RequiredPDFS/UNI-ATLAS Programmers Guide [532 kB] PMC-1980585 2002-02-07 
Locked Document, Log In RequiredPDFDSLAM Apps Note: Signal Integrity and Timing Simulation for the VORTEX Chipset [1.70 MB] PMC-1990816 2000-11-14 

Errata

Locked Document, Log In RequiredPDFS/UNI-ATLAS-1K800 Datasheet Errata [330 kB] PMC-2011076 2002-08-06 

Software Documentation

Locked Document, Log In RequiredPDFVORTEX Chipset Driver Design Specification [1.23 MB] PMC-1991216 2002-11-25 
Locked Document, Log In RequiredPDFS/UNI-ATLAS Driver Manual [815 kB] PMC-2000949 2002-01-17 

Software

Locked Document, Log In RequiredPDFS/UNI-ATLAS Device Driver [162 kB] PMC-2001241 rel 1.0  2002-03-04 

White Papers

PDFVORTEX Chip Set Introduction [392 kB] PMC-1990712 1999-07-21 

Technical Overview

Locked Document, Log In RequiredPDFS/UNI-APEX/ATLAS-1K800 Technical Overview [443 kB] PMC-2010379 2001-05-09 

Features

  • Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting and OAM requirements for 1024 VCs (virtual connections).
  • Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bi-directional cell transfer rate of 1.42x10 6 cell/s.
  • Ingress input interface supports an 8 or 16 bit PHY interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).
  • Ingress output interface supports an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface (Utopia Level 1) to a switch fabric.
  • Egress input and output interfaces support an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).
  • Compatible with the PM7329 S/UNI APEX 1K800 Traffic Manager, and PMC-Sierra's VORTEX Architecture.
  • Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing.
  • Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM and OAM-PM processing. Per-PHY output buffering scheme resolves the head-of-line blocking issue.
  • Includes a FIFO buffered 16-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device.
  • Supports DMA access for cell extraction.
  • The UTOPIA and external SRAM interfaces are 52 MHz max.

POLICING

  • ITU-I.371, ATM Forum TM4.0 compliant, per-VC programmable dual leaky bucket policing with a programmable action (tag, discard, or count only) for each bucket, each with 3 programmable 16 bit non-compliant cell counts.
  • Per-PHY single leaky bucket policing with a programmable action (tag, discard, or count only).
  • Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging.

OAM

  • ITU-I.610 compliant OAM on both Ingress and Egress directions.
  • Complete Fault Management (AIS, RDI, CC) processing, for VP/VC, Segment/End-to-end flows on all VCs.
  • Complete Performance Monitoring processing, for VP/VC, Segment/End-to-end, Forward/Backward flows, on 256 Bi-directional VCs.

CELL COUNTING

  • Per-VC counts include CLP0 cells, CLP1 cells, policing violations.
  • Per-PHY counts include CLP0 cells, CLP1 cells, OAM cells, errored OAM cells, unassigned/invalid cells and policing violations.
  • Per-device counts include total cells received/transmitted, and physical layer cells.

PACKAGING

  • Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
  • Low power 0.35 micron, 3.3V CMOS technology with a 3.3V UTOPIA (SCI-PHY), 3.3/5V Microprocessor I/O interfaces and 3.3V external synchronous SRAM interfaces.
  • Packaged in 432-pin ball grid array (BGA) package.

Applications

  • Mini Digital Subscriber Loop Access Multiplexer (Mini-DSLAM).
  • Subscriber Access Equipment.
  • Digital Loop Card Traffic Aggregation.
 
 
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