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PM7326 S/UNI® APEX
ATM and Packet/Frame Traffic Manager/Switch

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Version Issue Date

Product Brief

PDFPM7326 S/UNI-APEX ATM/PACKET Traffic Manager and Switch Short Form Data Sheet [59 KB] PMC-1990146 1999-04-26 

Reference Design

Locked Document, Log In RequiredPDFDSLAM Reference Design: Core Card [9.82 MB] PMC-1990815 2000-12-15 
Locked Document, Log In RequiredPDFDSLAM Line Card Software Reference Design [258 kB] PMC-2000504 2000-11-14 
Locked Document, Log In RequiredPDFDSLAM WAN Card Software Reference Design [241 kB] PMC-2000684 2000-11-14 

Data Sheet

Locked Document, Log In RequiredPDFATM/Packet Traffic Manager and Switch (S/UNI-APEX) Data Sheet [4.80 MB] PMC-1981224 2002-10-23 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM7326 S/UNI-APEX [919 kB] PMC-2020364   2003-10-06 
Locked Document, Log In RequiredPDFS/UNI-APEX Hardware Programmers Guide [465 kB] PMC-1991454 2002-07-02 
Locked Document, Log In RequiredPDFDSLAM Apps Note: Signal Integrity and Timing Simulation for the VORTEX Chipset [1.70 MB] PMC-1990816 2000-11-14 

Errata

Locked Document, Log In RequiredPDFVORTEX Chipset Driver Errata [241 kB] PMC-2010858 2003-04-01 
Locked Document, Log In RequiredPDFS/UNI-APEX Errata [467 kB] PMC-1991770 2000-04-11 
Locked Document, Log In RequiredPDFS/UNI-APEX Driver Errata [147 kB] PMC-2012043 2001-09-20 

Software Documentation

Locked Document, Log In RequiredPDFVORTEX Chipset Driver Design Specification [1.23 MB] PMC-1991216 2002-11-25 
Locked Document, Log In RequiredPDFS/UNI-APEX (ATM/Packet Traffic Manager and Switch) Driver Manual [6.07 MB] PMC-1991727 2000-05-24 

Software

Locked Document, Log In RequiredPDFS/UNI-APEX Device Driver [217 kB] PMC-991578 rel 1.0  2002-04-08 
Locked Document, Log In RequiredPDFVORTEX Chipset Driver [672 kB] PMC-2000781 Rel 1.0  2002-11-25 

White Papers

PDFVORTEX Chip Set Introduction [392 kB] PMC-1990712 1999-07-21 

Models

Locked Document, Log In RequiredPDFS/UNI-APEX [25 kB] 1.03  1999-08-16 

Technical Overview

Locked Document, Log In RequiredPDF S/UNI-APEX Technical Overview [605 kB] PMC-1981024 2000-10-05 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM7326 S/UNI-APEX Revision A PMC-1991192 1999-12-20 

Features

  • ATM (fixed length cell) and packet/frame traffic manager and switch.
  • 2048 line ports, 4 WAN ports, and a high speed microprocessor port. Any port to any port switching for 64k independent connections.
  • Manages up to 256k cell (16M byte) data buffer and 4M byte context memory shared over all ports.
  • Configurable progressive throttling of buffer consumption, with memory reservation under high consumption. Supports ABR with EFCI marking.
  • Buffer congestion controlled via Partial Packet Discard, Early Packet Discard (PPD/EPD). Cell at a time discard also supported.
  • For frame/packet flows:
    • Supports external wire speed HDLC processor, SAR, and flow classifier via packet-contiguous queuing and scheduling.
    • Error indication in AAL5 EOM trailer (set by SAR or classifier) can invoke errored packet discard, thereby eliminating need for packet buffers in external devices.
  • Traffic queuing algorithm is highly configurable on a per connection, per class, and per port basis.
  • Configurable scheduling of 4 classes of service on every port, with rate shaping available for the 4 WAN ports. Configurable traffic parameters enabling a mix of CBR, VBR, GFR, and UBR classes.
  • Configurable OAM cell queuing and special handling on all ports.
  • VPI/VCI header mapping.
  • Supports 700 Mb/s ingress traffic and 700 Mb/s egress traffic aggregated across all ports.
  • Low power 3.3/2.5V CMOS.
  • Standard 5 pin P1149 JTAG port.
  • 352 ball SBGA, 35mm x 35mm.

Bus Interfaces

  • 8/16 bit, 52 MHz UTOPIA L2 bus.
  • Line side:
    • Enhanced UTOPIA Tx master supports 2048 ports. Rx master supports 32 ports.
    • Or single port slave.
  • WAN side:
    • Master (with optional cell length expansion) supports 4 ports.
    • Or single port slave.

Microprocessor Interface

  • 66 MHz, 32 bit address/data bus capable of single or burst access to internal registers and cell buffers.
  • Supports cell/packet transfer to/from any port, with CRC32 and CRC10 calculation supported in hardware.
  • Works seamlessly with S/UNI VORTEX and S/UNI DUPLEX to implement a system-wide embedded communication channel.

Congestion Control

  • Traffic discard thresholds configurable per connection (independent CLP0 and CLP1 thresholds), per class, per port, and per direction.
  • Guaranteed Frame Rate (GFR) implemented via CLP0 minimum buffer size reservation per connection.

Queuing & Scheduling

  • 64k traffic staging queues (one per connection) individually assignable to any CoS on any port.
  • 8k + 20 scheduling queues: 4 CoS queues per port, 2048 line ports, 4 WAN ports, and 1 processor port.
  • Each port's queuing and scheduling configurable as cell at a time or frame at a time.
  • Connections are scheduled into each class queue using configurable weighted fair queuing (cell mode), or FIFO (frame mode).
  • Classes are scheduled into ports using strict priority with configurable minimum bandwidth reservation.
  • Ports are scheduled onto their corresponding bus using a configurable weighted interleaved round robin algorithm.
  • On the WAN ports: rate shaping, individually configured per connection, within four classes.

Accounting

  • Per connection CLP0/CLP1 upstream/downstream Tx counts.
  • Error statistics accumulation.
  • CLP0/CLP1 cell discard counts with indication of connection ID of last cell discarded.

Applications

  • Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM).
  • ATM switch port.
  • Multiservice access multiplexer.
  • UMTS wireless base stations.
 
 
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