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PM7325 S/UNI® ATLAS™ 3200
2.488 Gbit/s S/UNI ATM Layer Solution

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Version Issue Date

Product Brief

PDF3200 Mb/s ATM Layer Solution Short Form [111 kB] PMC-1990444 2  2000-03-27 

Reference Design

Locked Document, Log In RequiredPDFS/UNI-ATLAS-3200 with S/UNI-MACH48 Reference Design [9.47 MB] PMC-2000718 1  2001-01-03 

Data Sheet

Locked Document, Log In RequiredPDFOC-48 SUNI-ATM Layer Solution Data Sheet [2.32 MB] PMC-1990553 5  2003-01-09 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM7325 S/UNI-ATLAS-3200 [421 kB] PMC-2020363   2004-01-22 
Locked Document, Log In RequiredPDFS/UNI-ATLAS-3200 Programmers Guide [1.92 MB] PMC-2001159 1  2000-12-12 
Locked Document, Log In RequiredPDFATM Protection Switching Using the S/UNI-ATLAS-3200 [726 kB] PMC-2010386 1  2001-09-24 
Locked Document, Log In RequiredPDFCascading ATLAS-3200S to Support More Than 64K VCS [442 kB] PMC-2010820 1  2001-04-30 

Errata

Locked Document, Log In RequiredPDFS/UNI ATLAS 3200 Rev B Device Errata [389 KB] PMC-2000259 7  2003-12-09 

Software Documentation

Locked Document, Log In RequiredPDFS/UNI ATLAS 3200 Driver Manual [609 kB] PMC-2011037 2  2003-01-31 

Software

Locked Document, Log In RequiredPDFPM7325 S/UNI ATLAS 3200 Device Driver [232 kB] PMC-2011029 rel 1.0  2003-01-31 

Models

Locked Document, Log In RequiredPDFS/UNI-ATLAS-3200 [41 kB] 1.03  2001-05-02 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM7325 S/UNI-ATLAS-3200 Revision B PMC-2010447 1  2001-04-10 

Features

  • Monolithic single chip device which handles ATM Layer functions for one direction including VPI/VCI address translation, cell appending, cell rate policing, cell counting and OAM requirements for 64 k VCs (virtual connections). Two or more PM7325 S/UNI® ATLAS 3200 devices can be cascaded to support additional VC's.
  • Instantaneous transfer rate of 3200 Mbit/s supports a cell transfer rate of 5.68x106 cells/s.
  • Can be configured as an Ingress mode device or an Egress mode device.
  • POS-PHY/UTOPIA Level 3 PHY and Switch interface supports a 32-bit 104 MHz interface. Extended cell format is supported (52 - 64 byte cell). Packets are not processed and are buffered and passed through transparently. Handles up to 48 logical PHY ports.
  • Supports a full duplex 16 bit 52 MHz SCI-PHY Backwards Cell Interface Port which allows an Ingress mode device and an Egress mode device to communicate and behave as a single bi-directional device.
  • Supports a 64-bit (with or without parity) 125 MHz External Pipelined ZBT SRAM interface.
  • Includes a FIFO buffered 32-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device.
  • Per-PHY output buffering scheme resolves the head-of-line blocking issue.
  • Ingress and Egress functions include flexible search engines that cover the entire PHYID/VPI/VCI address range, dual leaky-bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing.

POLICING

  • ITU-I.371, ATM Forum TM4.1 compliant, per-VC programmable dual leaky-bucket policing with a programmable action (tag, discard, or count only) for each bucket, each with three programmable 16 bit non-compliant cell counts.
  • Per-PHY single leaky-bucket policing with a programmable action (tag, discard, or count only).
  • Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging.

OAM

  • ITU-I.610 (1999) compliant OAM on both Ingress and Egress directions.
  • Complete Fault Management (AIS, RDI, CC) processing, for VP/VC, Segment/End-to-end flows on all VCs.
  • Complete Performance Monitoring processing, for VP/VC, Segment/End-to-end, Forward/Backward flows, on 512 Uni-directional VCs.
  • Per-PHY AIS/RDI generation.

CELL COUNTING

  • Per-VC counts include CLP0 cells, CLP1 cells, OAM cells, RM cells, and invalid cells, cells violating the contract and total AAL5 frames.
  • Per-PHY counts include CLP0 cells, CLP1 cells, OAM cells, errored OAM cells, unassigned/invalid cells and policing violations.
  • Per-device counts include total cells received/transmitted, and physical layer cells.

PACKAGING

  • Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes.
  • Implemented in low power, 0.18 micron, 1.5 V CMOS technology with 2.5 V embedded DRAM, 2.5 V external SRAM interface, and 3.3 V external interfaces (excluding the SRAM interface).
  • Packaged in a 768 pin Tape Ball Grid Array (TBGA) package.

DEVICE INTERNETWORKING

  • Other PMC-Sierra devices that implement the POS-PHY Level 3 interface include:
    • PM3386: SUNI 2xGE - Dual gigabit ethernet controller.
    • PM3387: SUNI 1xGE - Single gigabit ethernet controller.
    • PM5354: SUNI MULTI 2x12 - Multi-rate OC-12x/OC-3c ATM and POS.
    • PM5358: SUNI 4x622 - Quad channel OC-12c ATM and POS.
    • PM5360: SUNI MULTI 48 - Multi-rate OC-48c/OC-12c/OC-3c ATM and POS.
    • PM5379: SUNI 4x155 - Quad channel OC-3c ATM and POS.
    • PM5380: SUNI 8x155 - Eight channel OC-3c ATM and POS.
    • PM5381: SUNI 2488 - Single channel OC-48c ATM and POS.
    • PM5382: SUNI 16x155 - Sixteen channel OC-3c ATM and POS.
    • PM5383: SUNI 12xJET - Twelve channel DS3 ATM and POS.
    • PM5386: SUNI 4xJET - Quad channel DS3 ATM and POS.
    • PM7390: SUNI MACH 48 - Multi service access device for channelized interfaces.

Applications

  • Core ATM switches.
  • Wide Area Network ATM Core and Edge Switches.
  • ATM Enterprise and Workgroup Switches.
  • Broadband Access Multiplexers.
 
 
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