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PM7324 S/UNI® ATLAS™
622 Mbit/s Full Duplex ATM Layer Device
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Features
GENERAL
- Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting and OAM requirements for 65536 VCs (virtual connections).
- Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bi-directional cell transfer rate of 1.42x106 cells/s.
- Ingress input interface supports an 8 or 16 bit PHY interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).
- Ingress output interface supports an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface (Utopia Level 1) to a switch fabric.
- Egress input and output interfaces support an 8 or 16 bit SCI-PHY (52 -64 byte cell) interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2).
- Compatible with a wide range of switching fabrics and traffic management architectures.
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- Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing.
- Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM and OAM-PM processing. Per-PHY output buffering scheme resolves the head-of-line blocking issue.
- Includes a FIFO buffered 16-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device.
- Supports DMA access for cell extraction.
- The UTOPIA and external SRAM interfaces are 52 MHz max.
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POLICING
- ITU-I.371, ATM Forum TM4.0 compliant, per-VC programmable dual leaky bucket policing with a programmable action (tag, discard, or count only) for each bucket, each with 3 programmable 16 bit non-compliant cell counts.
- Per-PHY single leaky bucket policing with a programmable action (tag, discard, or count only).
- Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging.
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- ITU-I.610 compliant OAM on both Ingress and Egress directions.
- Complete Fault Management (AIS, RDI, CC) processing, for VP/VC, Segment/End-to-end flows on all VC's.
- Complete Performance Monitoring processing, for VP/VC, Segment/ End-to-end, Forward/Backward flows, on 256 Bi-directional VC's.
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CELL COUNTING
- Per-VC counts include CLP0 cells, CLP1 cells, policing violations.
- Per-PHY counts include CLP0 cells, CLP1 cells, OAM cells, errored OAM cells, unassigned/invalid cells and policing violations.
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- Per-device counts include total cells received/transmitted, and physical layer cells.
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PACKAGING
- Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
- Implemented in low power, 0.35 micron, 3.3 Volt CMOS technology with 5 Volt tolerant and microprocessor interface, 3.3V UTOPIA and external synchronous SRAM interfaces.
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- Packaged in 432 pin ball grid array (BGA) package.
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Applications
- ATM Access Switches and Multiplexers
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- ATM Enterprise and Edge Switches
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S/UNI-ATLAS Short Form Data Sheet [59 kB] PMC-1980489 
S/UNI-ATLAS Device Driver [162 kB] PMC-2001241 
Boundary Scan Description Language (BSDL) Source Code for the PM7324 S/UNI-ATLAS Device PMC-1991250