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PM7306 FREEDM™ 84A1024L
Frame Engine and Datalink Manager
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Features
GENERAL
- Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for
line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s.
- Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via
HDLC termination and full packet store of the data within the HDLC structure.
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- Supports 2 levels of priority queueing, with fragment interleaving, in the egress direction for single HDLC channels.
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MULTILINK PPP AND FRAME RELAY BUNDLES
- Capable of supporting fragment sizes from 4 to 9.6 Kbytes.
- Supports up to 168 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels.
- Support for up to 300ms of intra bundle skew in the receive direction when supporting the minimum fragment size.
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- Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable per connection. Optionally, full packet transfers are
supported on a per connection basis.
- Supports RFC 1990 and RFC 2686 for ML-PPP bundles.
- Supports FRF-12 and FRF-16 for MLFR bundles.
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PPP
- Support for 16 COS levels in accordance with RFC 2686.
- Either 12 bit or 24 bit sequence number, with short and long fragment header formats, is supported.
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- Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface.
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PPP OVER FRAME RELAY
- Supports RFC 1973 PPP in Frame Relay.
- Fragmentation and re-assembly supported for PPP over FR type encapsulations.
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- Supported for both single link and multilink bundles.
- Accepts FRF-12 end-to-end fragments on HDLC channels configured in this mode.
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FRAME RELAY
- Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols.
- The lookup algorithm can support a maximum of 16 K connection identifiers (CIs) amongst all channels in use.
- Control frames are identified and forwarded to Any-PHY interface.
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- 12 bit sequence numbers supported.
- FECN, BECN, and DE ingress processing as per FRF.12.
- Supports End-to-End FRF.12 fragmentation for single HDLC channels.
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HDLC
- Support for up to 1024 bidirectional HDLC channels, with individual HDLC channel speeds ranging from 56 Kbit/s
to 52 Mbit/s. In a channelized application, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1)
and from 1 to 31 (for E1).
- The 1024 HDLC channels can be assigned to a mixture of physical links via the 19.44 MHz or 77.76 MHz SBI bus. The SBI transports the equivalent
of 3 STS-1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s or 1 DS3.
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- For each channel, supports programmable flag sequence detection and generation, bit stuffing and destuffing, and validation and generation
of either CRC-CCITT or CRC-32 frame check sequences.
- For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.
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INTERFACES
- 104 MHz, 8 bit Any-PHY Level 3 or 52 MHz Any-PHY Level 2 packet interface for transfer of packet, frame or fragment data using an external
controller. The interface is capable of supporting full datagram transfer on a per Any-PHY channel basis, or fragmented packets or frames on a per
Any-PHY channel basis.
- A 19.44 MHz or 77.76 MHz SBI bus supporting up to 84 links.
- 3 separate clock and data interfaces to support 3 links of arbitrary data rate up to 52 MHz (e.g., DS3/E3). The device can
be configured to process data from either the clock and data interfaces or from the SBI on a per clock-data-link/SPE basis.
- A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage.
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- A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data. structures.
- A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storage.
- Provides a standard 5 signal P1149.1 JTAG test port for boundary scan.
- A 32-bit microprocessor interface for configuration and status monitoring.
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TECHNOLOGIES
- 40 mm x 40 mm, 520 pin (1.27 mm pitch) enhanced ball grid array (SBGA) package.
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- Low power 0.18 mm CMOS technology using 1.8 V core power and 3.3 V I/O.
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Applications
- Wireless Base Station Controllers or Radio Network Controllers.
- Enterprise, Edge and Core Routers.
- Multi-Service Edge aggregation equipment.
- IETF PPP interfaces for routers.
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- Frame Relay interfaces for ATM or Frame Relay switches and multiplexers.
- FUNI or Frame Relay service internetworking interfaces for ATM switches and multiplexers.
- Internet/Intranet access equipment.
- Multi-service DSLAM equipment.
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PM7306 FREEDM 84A1024L Frame Engine and Datalink Manager Product Brief [190 KB] PMC-2050683 