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PM6341 E1XC
E1 Transceiver with Analog LIU

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Version Issue Date

Product Brief

PDFE1XC Short Form Data Sheet [42 kB] PMC-1920109 6  1998-03-11 

Data Sheet

Locked Document, Log In RequiredPDFE1XC Data Sheet [934 kB] PMC-1910419 8  1998-07-20 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM6341 E1XC [745 kB] PMC-2020353   2003-10-06 
Locked Document, Log In RequiredPDFMeeting ETS 300 011 Requirements using the E1XC [308 kB] PMC-1951128 3  1998-04-14 

Software

Locked Document, Log In RequiredPDFE1XC Device Driver [114 kB] Rev 4.12  2002-04-08 

Features

    GENERAL

    • Monolithic single chip device which integrates a full-featured E1 framer with on-chip analog line interface.
    • Provides frame synchronization and frame generation for a G.704/G.706 2048 Kbit/s signal with capability to support the optional signalling and CRC multiframes.
    • Supports HDB3 or AMI line coding and accepts gapped data streams to support higher rate demultiplexing.
    • Supports both 75 ohm and 120 ohm G.703 line interface.
    • Provides Channel Associated Signalling extraction/insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion and up to 3 multiframes of signalling debounce on a per channel basis.
    • Optionally extracts/inserts the datalink from/to timeslot 16 to receive/transmit Common Channel Signalling.
    • Pin compatible with the PM4341A T1XC single chip T1 transceiver. Application compatible with the PM7345 S/UNI PDH ATM Physical Layer Interface.
    • Provides an 8-bit microprocessor bus interface for configuration, control and status monitoring.
    • Low-power CMOS technology.
    • Available in a high density 80-pin (14 by 14mm) PQFP or in a 68-pin PLCC package.

    RECEIVE SECTION

    • Provides indications of loss of signal, loss of frame alignment (OOF), loss of signalling multiframe alignment and loss of CRC multiframe alignment.
    • Declares red and AIS alarms using Q.516 recommended integration periods
    • Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for CRC-4 errors, Far End Block Errors, Frame sync errors, and Line Code Violations.
    • Provides an integral HDLC/LAPD interface which may be used for terminating a CCS or National Bits datalink.
    • Provides a two frame elastic store for jitter and wander attenuation.
    • Provides programmable trunk conditioning on a per channel basis.

    TRANSMIT SECTIONS

    • Supports transmission of AIS, timeslot 16 AIS, remote alarm signal or remote multiframe alarm signal.
    • Provides an integral HDLC/LAPD interface which may be used for generating a CCS or National Bits datalink.
    • Provides an integrated digital phase locked loop for generation of a low jitter transmit clock.
    • Provides a FIFO buffer for jitter attenuation and rate conversion.
    • Provides programmable trunk conditioning which forces trouble code substitution and signalling conditioning on a per channel basis.

    Applications

    • E1 & E3 Multiplexers
    • Digital Loop Carriers
    • E1 Frame Relay Interfaces
    • E1 ATM UNI Interfaces
    • E1 Channel Service Units (CSUs) and Data Service Units (DSUs)
    • Digital Access and Cross-Connect Systems (DACS) and Electronic Digital Cross-Connect Systems (EDSX)
    • SDH Add/Drop Multiplexers (ADM)
    • ISDN Primary Rate Interfaces (PRI)
    • Digital Private Branch Exchanges (PBX)
    • E1 & E3 Test Equipment
     
 
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