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PM5390 S/UNI® 9953
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
Documents
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Please contact apps@pmc-sierra.com to gain access to the following
design support documents for PM5390 (S/UNI-9953) and PM5392 (S/UNI 9953-POS)
| Document Number |
Document Name |
| PMC-2030176
| S/UNI 9953 Datasheet Errata for Revision C
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| PMC-2030457
| S/UNI 9953-POS Data Sheet Errata for Revision A
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| PMC-2031371
| Flowtherm detailed model for PM5390
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| PMC-2010750
| Signal Integrity for PMC-Sierra 3.125/2.488/1.5GBPS Links
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| PMC-2030374
| BSDL File for S/UNI 9953
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| PMC-2011472
| PM5390 S/UNI 9953 and and PM5392 S/UNI 9953-POS Device Driver Manual
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| PMC-2020554
| S/UNI-9953 and PM5392 S/UNI-9953-POS Device Driver
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| PMC-2011362
| Chess-II Thermal Management Considerations
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| PMC-2011949
| S/UNI 9953 Device Quick Start Application Note
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| PMC-2011381
| Quad OC-48 Line Card Reference Design and Schematics
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| PMC-2011046
| Interfacing to SFI-4 on Xenon
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The customer support website also gives you access to a number of useful SPI4.2 (PL4) Application Notes
Features
- Provides WAN Interface Sub-layer (WIS), Physical Coding Sub-layer (PCS), and Media Access Controller (MAC) functionality for OC-192c rate 10 Gigabit Ethernet WAN PHY datastream.
- Provides PCS and MAC layer functionality for 10.3 Gbit/s 10 Gigabit Ethernet LAN PHY datastream.
- Supports framing, scrambling/descrambling and pointer processing for the following:
- STS-192c (STM-64-64c).
- 4 x STS-48c (4 x STM-16-16c).
- STS-192 (STM-64) channelized down to STS-48c (STM-16c).
- Supports alarm signal insertion/detection, B1/2/3 processing and insertion/termination of SONET Section/Line/Path overhead bytes (or SDH equivalents).
- Provides ATM and POS payload processing for:
- STS-192c (STM-64-64c)
- 4 x STS-48c (4 x STM-16-16c).
- STS-192 (STM-64) channelized down to STS-48c (STM-16c).
INTERFACES
- Provides SATURN POS-PHY Level 4 16-bit LVDS System-side Interface (clocked at 700 MHz nominal).
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- Directly connects to optics via 16 bit by 622 MHz OIF SFI-4 (OIF99.102) or 16 bit by 622/645 MHz IEEE P802.3ae XSBI line-side interfaces.
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POS/ATM
- Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Rec. I.432.
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- Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).
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10 GIGABIT ETHERNET
- Implements 10 Gigabit Ethernet WAN and LAN PHY according the IEEE P802.3ae standard currently under development.
- Provides standard IEEE P802.3ae 10 Gigabit Ethernet Media Access Controller (10GMAC) for frame verification.
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- Implements IEEE P802.3ae 64B/66B Physical Coding Sub-layer (PCS).
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10 GIGABIT ETHERNET MAC
- Verifies frame integrity (FCS and length checks).
- Provides egress Ethernet frame encapsulation (pads to min. size, add preamble, IFG and CRC generation).
- Supports VLAN tagged frames.
- Provides eight exact-match address filters to filter frames based on SA, DA or VID.
- Provides 64-bin hash based algorithm to filter multicast addresses.
- Minimum frame size of 64 bytes.
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- Provides statistics counters to support RMON/SNMP.
- Supports jumbo frames up to 9.6 Kbytes.
- Programmable inter-packet gap (IPG).
- Implements in-band PAUSE flow-control and provides support for out-of-band flow control.
- Upper layer device can flow-control using dedicated pins or host signaling to cause generation of a PAUSE frame.
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GENERAL
- Provides internal FIFOs (16 KB ingress, 20 KB egress) to accommodate system latencies.
- Provides line-side and system-side loopbacks for system level diagnostic capability.
- Provides support for automatic protection switching (APS) via two 16-bit LVDS 777.76 MHz ports.
- Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
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- Standard 5 signal P1149.1 JTAG test port.
- Low power 1.8 V CMOS core logic with 3.3 V CMOS/TTL compatible digital inputs and digital outputs.
- Industrial temperature range (-40 °C to +85 °C).
- 1152 pin FCBGA package.
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DEVICE INTERWORKING
- Other PMC-Sierra devices that implement the POS-PHY Level 4 interface include:
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POS-PHY LEVEL 4 INTERFACE
- Designed to transmit cells, packets or frames between physical and data-link layer devices.
- Supports mixed traffic protocols on a channel by channel basis.
- Requires less pins and draws less power than other 10 Gigabit interface options.
- Compliant with the following standards:
- Optical Internetworking Forum – System Physical Interface Level 4 Phase II (SPI-4 Phase II).
- ATM Forum – Frame Based ATM Interface Level 4 (ATMF0161.00).
- SATUR POS-PHY Level 4, Issue 6, March 2001.
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Applications
- Edge and Core Routers.
- Multi-Service (Multi-Protocol) Switches.
- Internet POP and Transport POP L2 Ethernet Switches.
- SONET/SDH add/drop multiplexers and optical cross-connects.
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- WAN and Edge ATM switches.
- Up-link cards.
- SONET/SDH ATM/POS and 10 Gigabit Ethernet test equipment.
- Emerging DPT, IPT, and GFP applications.
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