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PM5380 S/UNI® 8X155
8 Channel 155Mbit/s ATM and Packet over SONET/SDH Physical Layer Device
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Features
GENERAL
- Single chip ATM and Packet over SONET/SDH 8-channel Physical Layer Device operating at 155.52 Mbit/s.
- Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to ITU Recommendation I.432.
- Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615 and RFC 1662.
- Processes eight duplex bit-serial 155.52 Mbit/s STS-3c/STM-1 data streams with on-chip clock and data recovery and clock synthesis.
- Complies with Bellcore GR-253-CORE (2000 Issue) jitter tolerance, jitter transfer (1995 Issue) and intrinsic jitter criteria.
- Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
- Provides UTOPIA Level 3 compatible 32-bit wide System Interface (clocked up to 104 MHz) with parity support for ATM applications.
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- Provides SATURN POS-PHY Level 3. 32-bit System Interface (clocked up to 104 MHz) for Packet over SONET/SDH (POS) and ATM applications.
- Provides support functions for 1+1 APS and 1:N operation.
- Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
- Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
- Low power 2.5/3.3 volt CMOS with 5-volt TTL compatible digital inputs and outputs. PECL inputs and outputs are 3.3 volt and 5 volt compatible.
- Industrial temperature range (-40.C to +85 °C).
- 520 pin Super BGA package.
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THE SONET RECEIVER
- Provides eight serial interfaces at 155.52 Mbit/s with clock and data recovery.
- Frames to and de-scrambles the received STS-3c/STM-1 streams.
- Interprets the received payload pointers (H1, H2) and extracts the STS-3c/STM-1 synchronous payload envelopes and path overheads.
- Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing.
- Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure.
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- Captures and de-bounces each synchronization status (S1) nibble in a readable register.
- Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
- Extracts the 16-byte or 64-byte section trace (J0/Z0) sequences and the 16-byte or 64-byte path trace (J1) sequences into internal register banks.
- Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer (LOP), path alarm indication signal (AIS-P), path remote defect indication (RDI-P), path extended remote defect indicator (extended RDI-P).
- Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors, line remote error indicates (REI-L), received path BIP-8 (B3) errors and path remote error indications (REI-P) for performance monitoring purposes.
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THE RECEIVE ATM PROCESSOR
- Extracts ATM cells from the received STS-3c/STM-1 payload using ATM cell delineation.
- Provides ATM cell payload de-scrambling.
- Performs header check sequence (HCS) error detection , and idle/unassigned cell filtering.
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- Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms.
- Counts number of received cells, idle cells, errored cells and dropped cells.
- Provides a UTOPIA Level 3 compatible 32-bit wide datapath interface (clocked up to 104 MHz) with parity support to read extracted cells from an internal 64 ATM cell FIFO buffer (4 cells per channel).
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THE RECEIVE POS PROCESSOR
- Supports packet based link layer protocols using byte synchronous HDLC framing like PPP, HDLC and Frame Relay.
- Performs self-synchronous POS data de-scrambling on the received STS-3c/STM-1 payload using the x43+1 polynomial.
- Performs flag sequence detection and terminates the received POS frames.
- Performs frame check sequence (FCS) validation for CRC-16.ISO-3309 and CRC-32 polynomials.
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- Performs control escape de-stuffing of the HDLC stream.
- Checks for packet abort sequence.
- Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks those exceeding the maximum length as errored.
- Provides a SATURN POS-PHY Level 3 compliant 32-bit datapath interface (clocked up to 104 MHz) with parity support to read packet data from a 2Kbyte FIFO buffer (256 bytes per channel).
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THE SONET TRANSMITTER
- Synthesizes the 155.52 MHz transmit clock from a 77.76 MHz reference.
- Provides eight differential PECL bit-serial interfaces at 155.52 Mbit/s.
- Inserts register programmable path signal labels (C2).
- Generates the transmit payload pointers (H1, H2) and inserts path overhead.
- Optionally inserts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or 64-byte path trace (J1) sequence from internal register banks.
- Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream.
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- Scrambles the transmitted STS-3c/STM-1 streams and inserts the framing bytes (A1, A2).
- Optionally inserts register programmable APS bytes.
- Provides support allowing two devices to implement 1+1 and 1:N APS.
- Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-24 codes (B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to allow performance monitoring at the far end.
- Allows forced insertion of all-zeros data (after scrambling) and the corruption of the section, line, or path BIP-8 codes for diagnostic purposes.
- Inserts ATM cells or POS frames into the transmitted STS-3c/STM-1 payload.
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THE TRANSMIT ATM PROCESSOR
- Provides idle/unassigned cell insertion.
- Provides HCS generation/insertion, and ATM cell payload scrambling.
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- Counts number of transmitted and idle cells.
- Provides a UTOPIA Level 3 compatible 32-bit wide datapath interface (clocked up to 104
MHz) with parity support for writing cells into an internal 64 ATM cell FIFO buffer (4 cells
per channel).
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THE TRANSMIT POS PROCESSOR
- Supports any packet based link layer protocol using byte synchronous HDLC framing like PPP, HDLC and Frame Relay.
- Performs self-synchronous POS data scrambling using the x43+1 polynomial.
- Encapsulates packets within a POS frame.
- Performs flag sequence insertion.
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- Performs byte stuffing for transparency processing.
- Performs frame check sequence generation using the CRC-16.ISO-3309 and CRC-32 polynomials.
- Aborts packets under the direction of the host or when the FIFO underflows.
- Provides a SATURN POS-PHY Level 3 compliant 32-bit wide datapath (clocked up to 104 MHz) with parity support to an internal 2Kbyte FIFO buffer (256 bytes per channel).
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THE APS/CROSSBAR SUPPORT
- Allows the two channels to be switched (crossbar) and/or bridged channels on the transmit direction at the SONET/SDH path level.
- With one S/UNI 8x155 device, supports up to four 1+1 APS interface or a single 1:4 APS interface. Supports channel aliasing at the path level.
- With two S/UNI 8x155 devices, supports up to eight 1+1 APS interfaces or a various 1:N APS interfaces up to a single 1:8 APS interface.
- Allows the eight channels to be switched (crossbar) on the receive direction at the SONET/SDH path level.
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- Provides two transmit differential PECL bit-serial interfaces at 622.08 Mbit/s to switched receive channels (crossbar) or source transmit channels (bridge) with a second S/UNI 8x155 device at the SONET/SDH path level.
- Provides two receive differential PECL bit-serial interface at 622.08 Mbit/s to switch receive channels (crossbar) or source transmit channels (bridge) with a second S/UNI 8x155 device at the SONET/SDH path level.
- Provides performance monitoring of bit errors across the two receive streams.
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- Other PMC-Sierra devices that implement the POS-PHY Level 3 interface include:
- PM3386: SUNI 2xGE - Dual gigabit ethernet controller.
- PM3387: SUNI 1xGE - Single gigabit ethernet controller.
- PM5354: SUNI MULTI 2x12 - Multi-rate OC-12x/OC-3c ATM and POS.
- PM5358: SUNI 4x622 - Quad channel OC-12c ATM and POS.
- PM5360: SUNI MULTI 48 - Multi-rate OC-48c/OC-12c/OC-3c ATM and POS.
- PM5379: SUNI 4x155 - Quad channel OC-3c ATM and POS.
- PM5381: SUNI 2488 - Single channel OC-48c ATM and POS.
- PM5382: SUNI 16x155 - Sixteen channel OC-3c ATM and POS.
- PM5383: SUNI 12xJET - Twelve channel DS3 ATM and POS.
- PM5386: SUNI 4xJET - Quad channel DS3 ATM and POS.
- PM7325: SUNI ATLAS 3200 - 2.488G ATM layer solution.
- PM7390: SUNI MACH 48 - Multi service access device for channelized interfaces.
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Applications
- WAN and Edge ATM switches.
- LAN switches and hubs.
- Packet switches and hubs.
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- Routers and Layer 3 Switches
- Network Interface Cards and Uplinks
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PM5380 S/UNI?8x155 8-Channel OC-3c ATM and POS Physical Layer Device Short Form Data Sheet [67 kB] PMC-2021288 
Configuration Guide for S/UNI-16x155, S/UNI-8x155 and S/UNI-4x155 [268 kB] PMC-2021321 
(BSDL) SOURCE CODE FOR THE PM5380 S/UNI-8X155 REV. A DEVICE [27 kB] PMC-2021202