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PM5356 S/UNI® 622 MAX
ATM OC-12c (622 Mbit/s) PHY

Documents

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Version Issue Date

Product Brief

PDFS/UNI-622-MAX Short Form Data Sheet [102 kB] PMC-1981279 2001-08-01 

Reference Design

Locked Document, Log In RequiredPDFS/UNI-622-POS Reference Design [2.55 MB] PMC-1981070 2000-02-28 

Data Sheet

Locked Document, Log In RequiredPDFS/UNI-622-MAX Long Form Data Sheet [1.19 MB] PMC-1980589 2002-11-22 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5356 S/UNI-622-MAX [597 kB] PMC-2020334   2003-10-06 

Errata

Locked Document, Log In RequiredPDFS/UNI-622-MAX Data Sheet Errata [84 KB] PMC-1990257 2004-02-09 

Software Documentation

Locked Document, Log In RequiredPDFSoftware Driver Manual for the S/UNI-622-MAX [233 kB] PMC-1981297 2002-08-27 

Software

Locked Document, Log In RequiredPDFSUNI-622-MAX Device Driver [22 kB] Rev 1.0  2002-04-08 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5356 S/UNI-622-MAX Device PMC-1990710 2000-05-10 

Features

GENERAL

  • ATM OC-12c (622 Mbit/s) PHY
  • Provides on-chip clock and data recovery and clock synthesis.
  • Exceeds Bellcore-GR-253 jitter tolerance and transmit jitter requirements.
  • Provides a generic 8-bit microprocessor interface for device control and register access.
  • Provides standard IEEE 1149.1 JTAG test port for boundary scan.

SONET RECEIVER

  • Recovers clock and data.
  • Frames to and descrambles recovered stream.
  • Filters and captures Automatic Protection Switch bytes (K1,K2) and detects APS byte failure.
  • Detects signal degrade and signal failure threshold crossing alarms.
  • Captures and debounces synchronization status byte (S1).
  • Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs.
  • Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI.
  • Provides divide by 8 recovered clock.
  • Provides 8 KHz receive frame pulses.

SONET TRANSMITTER

  • Provides a transmit frame pulse input to align the transport frame to a system reference.
  • Provides transmit clock as timing reference for transmit outputs.
  • Inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
  • Inserts PAIS, PRDI, LAIS and LRDI.
  • Scrambles transmit data stream.

ATM PROCESSOR

  • Implements the ATM Forum User Network Interface Specification.
  • Inserts and extracts ATM cells into and from the SONET SPE.
  • Performs cell payload scrambling and descrambling.
  • Provides UTOPIA Level 2 and 8-bit 100 MHz UTOPIA Level 3 compliant system interfaces.
  • Provides synchronous 4 cell transmit and receive FIFO buffers.

PACKAGING

  • Implemented in low power 3.3 Volt CMOS technology.
  • Packaged in a 304 pin ball grid array (BGA) package.
  • Industrial temperature range (-40°C to +85°C).

Applications

  • Enterprise and Edge ATM switches.
  • ATM switches and hubs.
  • Multiprotocol switches.
 
 
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