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PM5351 S/UNI® 155 TETRA
Quad 155 Mbit/s ATM and Packet Over SONET/SDH

Documents

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Version Issue Date

Product Brief

PDFS/UNI-155-TETRA Short Form Data Sheet [83 kB] PMC-1980862 3  2001-08-01 

Reference Design

Locked Document, Log In RequiredPDFS/UNI-TETRA Reference Design with WAN Clocking [1.30 MB] PMC-1980322 3  2000-01-04 
Locked Document, Log In RequiredPDFATM Switch Using S/UNI-ATLAS, QRT, and QSE [922 kB] PMC-1990330 2  1999-07-23 
Locked Document, Log In RequiredPDFS/UNI-155-TETRA with S/UNI ATLAS Reference Design [974 kB] PMC-1991709 1  2001-09-10 

Data Sheet

Locked Document, Log In RequiredPDFSaturn User Network Interface (155 TETRA) Telecom Standard Product Data Sheet [1.56 MB] PMC-1971240 8  2005-11-28 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5351 S/UNI-155-TETRA [954 kB] PMC-2020331   2003-10-06 

Errata

Locked Document, Log In RequiredPDFS/UNI-TETRA Data Sheet Errata [541 kB] PMC-1981004 10  2002-11-12 

Software Documentation

Locked Document, Log In RequiredPDFSoftware Driver for the S/UNI-TETRA [146 kB] PMC-1981217 1  1998-12-02 

Software

Locked Document, Log In RequiredPDFSUNI-155-TETRA Device Driver [29 kB] Rev 1.0  2002-04-08 

Models

Locked Document, Log In RequiredPDFS/UNI-TETRA [33 kB] 1.10  2001-07-06 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5351 S/UNI-TETRA Device PMC-1990337 2  2000-09-28 

Features

  • Quad channel ATM and Packet over SONET OC-3c (155 Mbit/s) PHY.
  • Provides on-chip clock and data recovery and clock synthesis.
  • Exceeds Bellcore-GR-253 jitter requirements.
  • Inserts and extracts ATM cells or POS packets into/from SONET SPE.
  • Filters and captures Automatic Protection Switch byes (K1 and K2) and detects APS byte failure.
  • Detects signal degrade and signal failure thresholds crossing alarms.
  • Captures and debounces synchronization status byte (S1).
  • Extracts and inserts the 16- or 64-byte section trace (J0) and path trace (J1) messages.
  • Extracts and inserts section/line data communication channels (DCC).
  • Provides circuitry to meet holdover, wander and long term stability.
  • Provides a generic 8-bit microprocessor interface for device control and register access.
  • Provides standard IEEE 1149.1 JTAG test port for boundary scan.

ATM

  • Implements the ATM Forum User Network Interface Specification.
  • Performs cell payload scrambling and descrambling.
  • Provides a UTOPIA Level 2-compliant system interface.
  • Provides synchronous 4-cell transmit and receive FIFO buffers.

PACKET OVER SONET

  • Generic design that supports packet based protocols like PPP, HDLC and Frame Relay.
  • Implements the PPP over SONET/SDH specification according to RFC 1619 and 1662 of the IETF.
  • Performs flag sequence detection and insertion.
  • Performs CRC-CCITT and CRC-32 FCS generation and validation.
  • Performs byte stuffing and destuffing.
  • Checks for minimum and maximum packet lengths.

PACKAGING

  • Low power, 3.3 V CMOS technology.
  • Packaged in a 304-pin Ball Grid Array (BGA) package.
  • Industrial temp. range (-40° to +85°C).

Applications

  • WAN and Edge ATM Switches
  • Multiprotocol Switches
  • Layer 3 Switches
  • Routers, Packet Switches, and Hubs
 
 
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