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PM5349 S/UNI® 155 QUAD
Quad channel ATM OC-3c (155 Mbit/s) PHY

Documents

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Version Issue Date

Product Brief

PDFS/UNI-155-QUAD Short Form Data Sheet [72 kB] PMC-1980863 1999-08-20 

Reference Design

Locked Document, Log In RequiredPDFS/UNI-155-QUAD Reference Design [370 kB] PMC-1980932 1999-11-04 

Data Sheet

Locked Document, Log In RequiredPDFSaturn User Network Interface (155-QUAD) Telecom Standard Product Data Sheet [991 KB] PMC-1971239 2005-11-24 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5349 S/UNI-155-QUAD [520 kB] PMC-2020329   2003-10-06 

Errata

Locked Document, Log In RequiredPDFS/UNI-Quad Data Sheet Errata [79 KB] PMC-1981005 2004-02-09 

Software Documentation

Locked Document, Log In RequiredPDFSoftware Driver for the S/UNI-QUAD [136 kB] PMC-1981295 1998-12-02 

Software

Locked Document, Log In RequiredPDFSUNI-155-QUAD Device Driver [24 kB] Rev 1.0  2002-04-08 

BSDL Files

PDFBoundary Scan Description Language (BSDL) Source Code for the PM5349 S/UNI QUAD Device (Revision G) [36 KB] PMC-1990338 2005-11-25 

Features

GENERAL

  • Quad channel ATM OC-3c (155 Mbit/s) PHY.
  • Provides on-chip clock and data recovery and clock synthesis.
  • Exceeds Bellcore-GR-253 jitter tolerance and transmit jitter requirements.
  • Provides a generic 8-bit microprocessor interface for device control and register access.
  • Provides standard IEEE 1149.1 JTAG test port for boundary scan.

SONET RECEIVER

  • Recovers clock and data.
  • Frames to and decrambles recovered stream.
  • Filters and captures Automatic Protection Switch bytes (K1,K2) and detects APS byte failure.
  • Detects signal degrade and signal failure threshold crossing alarms.
  • Captures and debounces synchronization status byte (S1).
  • Counts received section BIP-8 (B1), line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs.
  • Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI.
  • Provides individual divide by 8 recovered clocks for each channel.
  • Provides individual 8 KHz receive frame pulses for each channel.

SONET TRANSMITTER

  • Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
  • Provides a single transmit frame pulse input to align the transport frames to a system reference.
  • Provides single transmit clock as timing reference for transmit outputs.
  • Inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
  • Inserts PAIS, PRDI, LAIS and LRDI.
  • Scrambles transmit data stream.
ATM PROCESSOR
  • Implements the ATM Forum User Network Interface Specification
  • Inserts and extracts ATM cells into and from the SONET SPE.
  • Performs cell payload scrambling and descrambling.
  • Provides a UTOPIA Level II compliant system interface.
  • Provides synchronous 4 cell transmist and receive FIFO buffers.

PACKAGING

  • Implemented in low power 3.3 Volt CMOS technology.
  • Packaged in a 304 pin ball grid array (BGA) package.
  • Industrial temperature range (-40°C to +85°C).

Applications

  • Enterprise and Edge ATM switches
  • ATM switches and hubs
  • Multiprotocol switches
 
 
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