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PM5348 S/UNI® 155 DUAL
2 independent SATURN-Compatible ATM PHY channels in 1 chip

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Version Issue Date

Product Brief

PDFS/UNI-155-DUAL Short Form Data Sheet [66 kB] PMC-1950446 1997-03-10 

Reference Design

Locked Document, Log In RequiredPDFS/UNI-155-DUAL ATM Reference Transceiver (DART) Board [3.36 MB] PMC-1960552 1997-01-21 

Data Sheet

Locked Document, Log In RequiredPDFS/UNI-155-DUAL Data Sheet [948 kB] PMC-1950919 1998-07-20 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5348 S/UNI-155-DUAL [376 kB] PMC-2020328   2003-11-06 
Locked Document, Log In RequiredPDFInterfacing the S/UNI-155-DUAL SCI-PHY to UTOPIA Level 2 Using Address Polling [120 kB] PMC-1960333 1996-11-29 

Errata

Locked Document, Log In RequiredPDFS/UNI-DUAL Data Sheet Errata [160 kB] PMC-1991432 2003-04-09 
Locked Document, Log In RequiredPDFS/UNI DART Board Errata [38 kB] PMC-1970631 1997-07-31 

Models

Locked Document, Log In RequiredPDFS/UNI-DUAL [21 kB] 1.01  1998-04-28 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5348 S/UNI-DUAL Device PMC-1960808 1996-08-22 

Features

  • Provides two independent SATURN-Compatible ATM PHY channels in one chip.
  • Provides hardware and software backwards compatibility with the industry-standard PM5346 S/UNI 155 LITE chip.
  • Implements the ATM transmission convergence (TC) sublayer according to ATM Forum specifications using the SONET/SDH 155.52 Mbit/s STS-3c/STM-1 and SONET 51.84 Mbit/s STS-1 formats.
  • NRZ data format supports category-5 unshielded twisted pair (UTP-5) or shielded twisted pair (STP) wiring and optical data link modules for fiber optic cable.
  • Includes on-chip clock recovery and clock synthesis, compliant to Bellcore and ITU-T requirements.
  • Operates in timing master or timing slave (loop timed LAN) modes.
  • Frames to SONET framing bytes (A1, A2), processes the section and line Bit Interleaved Parity (B1, B2) and the Far-End Block Error (Z2) bytes.
  • Interprets the H1, H2 and H3 payload pointer bytes.
  • Processes the SONET path overhead BIP-8 (B3), signal label (C2) and path status (G1) bytes.
  • Allows for protection switching by monitoring the APS (K1, K2) bytes, bit error rate thresholds and far-end synchronization status (S1) bits and providing interrupts when error conditions are detected.*
  • Inserts and extracts ATM payloads using ATM cell delineation.
  • Provides on-chip four-cell FIFO buffers in both transmit and receive paths.
  • Operates with a backwards compatible dual 8-bit plus parity or a multi-PHY compatible 16-bit plus parity* SATURN-Compliant Interface for PHYsical layer devices (SCI-PHY(TM)).
  • Cell interface is also compatible with ATM Forum Level 2 Utopia direct-mode specifications.
  • Provides a generic 8-bit microprocessor bus interface for configuration, control and monitoring.
  • Provides TTL/CMOS compatible inputs and outputs and differential PECL inputs.
  • Low power, +5 Volt CMOS technology.
  • Packaged in a 28x28 mm 160-pin plastic quad flat pack (PQFP).
  • Note: *Indicates new features not provided on S/UNI 155 LITE.

Applications

  • ATM Switches and Hubs
  • ATM Routers
 
 
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