Need More Information?

PM5347 S/UNI® PLUS
Enhanced ATM SATURN® User Network Interface for 51 and 155 Mbit/s

Documents

> Are you seeing all your results?
If you are a PMC-Sierra Customer or Partner you may have permission to see additional results.
Please log in to display additional results.

Version Issue Date

Product Brief

PDFS/UNI-155-PLUS Short Form Data Sheet [152 kB] PMC-1930909 1999-04-19 

Reference Design

Locked Document, Log In RequiredPDFOCTAL-PLUS Reference Design [13.44 MB] PMC-1960553 1998-04-09 
Locked Document, Log In RequiredPDFAutomatic Protection Switching (APS) Software Reference Design [158 kB] PMC-1971116 1998-04-09 

Data Sheet

Locked Document, Log In RequiredPDFSATURN USER NETWORK INTERFACE (155 MBIT/S & 51 MBIT/S, [1.58 MB] PMC-1941033 2005-11-24 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5347 S/UNI-155-PLUS [394 kB] PMC-2020327   2003-11-06 
Locked Document, Log In RequiredPDFS/UNI-155-PLUS Board Layout Application Note [123 kB] PMC-1960545 1997-09-18 
Locked Document, Log In RequiredPDFMulti-PHY Adapter for OCTAL-PLUS [2.40 MB] PMC-1970438 1998-04-01 

Errata

Locked Document, Log In RequiredPDFS/UNI-155-PLUS Data Sheet Errata [88 KB] PMC-1990127 2007-06-01 

Models

Locked Document, Log In RequiredPDFS/UNI-PLUS [23 kB] 1.02  1998-04-18 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5347 S/UNI-PLUS Device [19 KB] PMC-1960757 2001-01-24 

Features

    GENERAL

    • Monolithic SATURN Compatible Asynchronous Transfer Mode (ATM) network interface.
    • Implements the ATM transmission convergence sublayer for ATM according to ATM Forum specifications and ITU-T recommendations using the SONET/SDH 155.52 Mbit/s format.
    • Also implements ATM Forum specified 'Mid-range PHY' rates of 51.52, 25.92 and 12.96 Mbit/s.
    • Includes on-chip clock recovery and clock synthesis at all rates. Clocking can be bypassed for use with external clock sources. Operates in timing master or timing slave (loop timed) modes.
    • Provides TTL compatible inputs and outputs. Provides differential pseudo-ECL compatible serial line side inputs. Supports Fiber Optic, Unshielded Twisted Pair and Shielded interfaces.
    • Processes all SONET/SDH UNI overhead.
    • Provides access to section and line data links and all additional transport and path overhead to allow additional external processing for full SONET/SDH Network-Node Interface (NNI) compliance.
    • Provides synchronous 8-bit or 16-bit SCI-PHY system side interface with 4 cell deep FIFO buffers in both transmit and receive paths with parity support.
    • Inserts and extracts ATM payloads using cell delineation.
    • Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
    • Software compatible with the PM5346 S/UNI 155 LITE and the PM5355 S/UNI 622.
    • Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes.
    • Low power, +5 Volt CMOS technology.
    • Packaged in a 208-pin (28x28 mm) PQFP with 0.5 mm pin pitch.
    • Industrial Temperature Range Operation (-40 °C to +85 °C).

    RECEIVE SECTION

    • Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure.
    • Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence into internal register banks. Extracts the DCC channels (D1-D3 and D4-D12) for optional external processing.
    • Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (RDI-L), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication signal (RDI-P) and loss of cell delineation (LCD).
    • Counts received section B1 errors, line B2 errors, line FEBEs, path B3 errors and path FEBEs for performance monitoring purposes.
    • Counts received cells written into the receive FIFO, received HCS errored cells that are discarded, and received HCS errored cells that are corrected and passed through the receive FIFO.

    TRANSMIT SECTION

    • Counts transmit cells read from the transmit FIFO.
    • Inserts a register programmable path signal label (C2).
    • Inserts path B3, path FEBE indications, line B2, line FEBE indications, section B1 to allow performance monitoring at the far end.
    • Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence from internal register banks.
    • Optionally inserts an externally generated section user channel (F1), order wire channels (E1, E2) and the DCC channels (D1-D3 and D4-D12) via serial interfaces.
    • Optionally inserts path AIS, path RDI, line AIS and line RDI.
    • Optionally inserts register programmable APS (K1, K2) and synchronization status (Z1) bytes.

    Applications

    • ATM Switching Systems
    • ATM Access Systems
    • LAN Switches, Hubs and Routers
    • ATM Test Equipment
    • SONET or SDH ATM Interfaces
     
 
This site's design is only visible in a graphical browser that supports web standards,
but its content is accessible to any browser or Internet device.