PM5337 ADM 622
Single Chip Add/Drop Multiplexer

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		Version	Issue Date
Product Brief
	PM5337 ADM 622 Integrated Add/Drop Multiplexer for 622 Mbit/s and 155 Mbit/s Short Form Data Sheet [46 KB] PMC-2030421	2	2004-09-15
Application Note
	Configuring SBI Compatible Devices [551 KB] PMC-2020180	6	2007-11-20
	Attaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246	3	2007-05-02
White Papers
	Application of Message Assisted Protection Switching (MAPS) to APS Architectures [402 KB] PMC-2021902	3	2003-09-22
	Generic Framing Procedure (GFP) [279 KB] PMC-2041083	2	2005-04-29
	Supporting VoIP over Ethernet over SONET/SDH [258 KB] PMC-2052545	1	2006-02-21
	Evolving Efficient Interconnects for High Density LIUs [143 KB] PMC-2040598	1	2004-06-09
Sales Collateral
	Notice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178	1	2006-10-19

Symbols/Footprints

	Version	Issue Date
PMC-2051176 PM5337 ADM 622 896 FCBGA CAD Symbols and Footprints [460 KB]	1	2005-06-15

Features

GENERAL

Fully integrated Solution for OC-3/STM-1 and OC-12/STM-4 Add/Drop or Terminal Multiplexers
Capable of ring completion in a single device (line protection mode) or as a two-chip solution (full redundancy mode)

Interfaces seamlessly with PMC-Sierra's broad portfolio of SONET/SDH transport devices
Integrated Cross-connect allows for future system expansion and incremental addition of transport interfaces

SONET/SDH INTERFACE

Multi-rate SONET/SDH Interface capable of operation at 155 or 622 Mbit/s
Integrated clock recovery allows direct interface to low-cost optical transceivers
Integrated clock synthesis generates line clock from 77.76 MHz reference
Auxiliary telecombus interface allows interface to alternate or secondary line side framer
Complies with Bellcore, ANSI, and ITU specifications for Jitter Tolerance, Transfer, and Generation

High order path processing to STS-1/AU-3/TU-3 level
Low order path processing to VT1.5/VT2/TU-11/TU-12 level
Full access to all SONET/SDH Overhead bytes
Integrated MAPS processing for fully automatic UPSR path selection

LOW-ORDER / HIGH-ORDER CROSS-CONNECT

Integrated 2.5G non-blocking memory based cross-connect supports anycast traffic
Support switching at STS/AU/VT/TU level and all legal concatenations

Integrated MAPS processing for automated protection switching

ADD/DROP PDH INTERFACES

28xT1 or 21xE1 framers with VT/TU Mapping or M13 Multiplexing

3xDS3, E3, and EC-1 framers and mappers with bi-directional performance monitoring and signaling

ADD/DROP DATA INTERFACE

Single 10/100/1000 or eight 10/100 EoS Interfaces
HDLC, X.86, or GFP Encapsulation
Low order and High order Virtual Concatenation with hitless LCAS

Grooming, Aggregation, and Policing
Ethernet OA&M packet insertion and extraction
Flexible Ethernet Header Filtering for VLAN & MPLS support

SYSTEM EXPANSION

Four serial 622M ESSI interfaces for expansion or connection to a mate ADM-622 device

Single multi-drop telecombus interface for expansion

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PM5337 ADM 622 Single Chip Add/Drop Multiplexer