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PM5333 ARROW 8xFE
8 Channel 10/100 Ethernet over SONET/SDH Mapping Device

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Version Issue Date

Product Brief

Locked Document, Log In RequiredPDFPM5333 ARROW 8xFE 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device Short Form Data Sheet [50 KB] PMC-2012677 5  2004-11-02 

Application Note

Locked Document, Log In RequiredPDFAttaching Passive Heat Sinks to Organic Flip Chip Packages [142 KB] PMC-2020246 3  2007-05-02 

White Papers

Locked Document, Log In RequiredPDFGeneric Framing Procedure (GFP) [279 KB] PMC-2041083 2  2005-04-29 
PDFEthernet Transport Services - The Current State of the Art [450 kB] PMC-2030897 1  2003-05-23 

Sales Collateral

Locked Document, Log In RequiredPDFNotice of Change - All FCBGA Packages to be Standardized to the HDBU Substrate Package Outline [695 KB] PMC-2062178 1  2006-10-19 

Technical Overview

Locked Document, Log In RequiredPDFRASIO 3G for SONET/SDH Backplanes Technology Brief [64 kB] PMC-2030933 1  2003-05-29 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped FilePMC-2060380 PM5333-FI ARROW 8xFE 672 FCBGA CAD Symbols and Footprints [451 KB]12006-03-01

Features

  • Maps up to eight channels of full-duplex 10/100M Ethernet into 622 Mbps SONET/SDH
  • Supports multiple encapsulation protocols for worldwide interoperability including GFP, LAPS, and flexible HDLC
  • Performs virtual and contiguous concatenation according to ITU-T G.707 and ANSI T1.105
  • Supports selection of STS-1/VC-3 virtual concatenation, VT1.5/VC-12 virtual concatenation or STS-3c on a per port basis
  • Generates and terminates High-Order and Low-Order SONET/SDH POH
  • Supports bandwidth provisioning in arbitrary steps of 1.6 Mbit/s (VT1.5) or 2.2 Mbit/s (VC-12)
  • Supports fully integrated hitless Link Capacity Adjustment Scheme (LCAS)
  • Supports up to 64 ms of differential delay

ETHERNET SUBSYSTEM

  • Provides integrated IEEE 802.3 compliant media access controllers (MAC)
  • Provides IEEE 802.3 compliant Ethernet management interface (MDIO)
  • Supports interfacing to full duplex 10/100M connections via SMII or SSSMII
  • Supports per Ethernet port loopback enabling S/W based client side fault isolation and monitoring
  • Supports loss-less IEEE 802.3 local flow-control
  • Provides per port Ethernet Statistics using 32-bit counters for frames and 40-bit counters for octets to ensure rollover compliance of 58 minutes as per IEEE 802.3
  • Supports frame delineation and generation with configurable IPG, preamble and CRC
  • Supports transparent transmission of VLAN tagged Ethernet frames
  • Supports frame sizes of 64 bytes to 9632 bytes
  • Supports programmable frame truncation from 1518 bytes to 9632 bytes
  • Supports programmable depth fullpacket store-and-forward buffers for burst tolerance and rate adaptation
  • Supports up to 512 Kbytes ingress buffering per port
  • Supports 23 Kbytes egress buffering per port

ENCAPSULATION

  • Supports the following encapsulation protocols on a per port basis:
    • ITU-T G.7041 Generic Framing Procedure (frame-based)
    • ITU-T X.86 Link Access Procedure for SDH (LAPS)
    • Flexible HDLC
  • Supports insertion and extraction of GFP Client Management Frames (CMF)
  • Supports insertion and extraction of LCP, NCP and BCP control frames

SONET/SDH SUBSYSTEM

  • Supports up to 8 virtual concatenation groups (VCGs)
  • Support High-Order (STS-1-Xv/VC-3-Xv & STS-3-Xv/VC-4-Xv) and Low-Order (VT1.5-Xv/VC-12-Xv) Virtual Concatenation
  • Supports STS-1/STM-0, STS-3c/STM-1 Contiguous concatenation
  • Supports High-Order POH processing and pointer interpretation for STS-1, STS-3c, AU-3 and AU-4
  • Supports Low-Order POH processing and pointer interpretation for VT1.5, TU-12 and TU-3
  • Provides on-chip data and clock recovery and clock synthesis for SONET/SDH ESSI interfaces
  • Supports High-Order POH insertion and extraction
  • Supports Low-Order POH insertion and extraction
  • Supports the following mapping formats:
    • C-12/ VC-12/ TU-12/ TUG-2/ TUG-3/ VC-4/ AU-4/ STM-1
    • C-12/ VC-12/ TU-12/ TUG-2/ VC-3/ AU-3/ STM-1
    • C-3/ VC-3/ TU-3/ TUG-3/ VC-4/ AU-4/ STM-1
    • C-3/ VC-3/ AU-3/ STM-1
    • C-4/ VC-4/ AU-4/ STM-1
    • VT1.5 SPE/ VT1.5/ STS-1 SPE/ STS-1
    • STS-1 SPE/ STS-1
    • STS-3c SPE/ STS-3c
  • Supports LCAS according to ITU-T G.7042
  • Provides per-serial link PRBS generation and detection
  • Integrated SONET/SDH Timeslot Interchange (STSI)
    • STS-1/AU-3 granular during SONET/SDH (AU-3) operation
    • AU-4 granular during SDH (AU-4) operation

GENERAL

  • Provides SMII, or source synchronous (SS-SMII) ports for connection to external Ethernet PHYs
  • Provides an MII Ethernet Management Interface (MDIO) for control and configuration of external Ethernet PHYs
  • Provides working and protect LVDScompatible CML interfaces:
    • 777.6 MHz Serial TelecomBus link with 8B/ 10B-based encoding
    • 622 MHz SONET/SDH Serial Interface (SSI) link with scrambled NRZ coding
  • Provides a general purpose 16-bit µp interface for configuration, management and statistics gathering
  • Provides an IEEE 1149.1 compliant JTAG test port for boundary scan

PACKAGING

  • Low power 1.2 V core with 2.5/ 3.3 V CMOS/ TTL I/O, 2.5 V SSTL_2 digital I/O
  • 27 x 27 mm 672 ball FCBGA package
  • Industrial temperature range (-40 °C to +85 °C).

Applications

  • Access and Metro Ethernet Add-Drop Multiplexers (ADM)
  • Multi-service Provisioning Platforms (MSPP)
 
 
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