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PM5316 SPECTRA™ 4 x 155
Monolithic four channel SONET/SDH Payload Extractor/Aligner

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Version Issue Date

Product Brief

PDFSPECTRA-4x155 Short Form Data Sheet [55 kB] PMC-2000327 2002-08-23 

Reference Design

Locked Document, Log In RequiredPDFSPECTRA-4X155 with TBS Reference Design [454 kB] PMC-1991245 2001-06-15 

Data Sheet

Locked Document, Log In RequiredPDFSPECTRA 4x155 ASSP Telecom Standard Product Data Sheet [1.79 MB] PMC-1990822 2005-11-24 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5316 SPECTRA-4x155 [1.09 MB] PMC-2020320   2005-09-22 
Locked Document, Log In RequiredPDFSONET/SDH Bit Error Threshold Monitoring [192 KB] PMC-1950820 2003-10-15 

Errata

Locked Document, Log In RequiredPDFSPECTRA 4x155 Production Release Errata [86 KB] PMC-2002110 2006-12-01 

Software Documentation

Locked Document, Log In RequiredPDFSPECTRA-4x155 Driver Manual [2.81 MB] PMC-2001693 2002-10-18 

Software

Locked Document, Log In RequiredPDFSPECTRA-4x155 Device Driver [134 kB] PMC-2001967 rel 1.0  2001-12-21 

Models

Locked Document, Log In RequiredPDFSPECTRA-4X155 [31 kB] 1.03  2001-07-17 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM5316 SPECTRA-4x155 Rev. A Device PMC-2001563 2001-03-12 

Features

  • Monolithic four channel SONET/SDH Payload Extractor/Aligner for use in STS-3 (STM-1/AU-3) or STS-3c (STM-1/AU-4) interface applications, operating at serial interface speeds of 155.52 Mbit/s.
  • Provides integrated clock recovery and clock synthesis to allow direct interface to optical modules.
  • Each channel provides termination for SONET Section and Line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of three STS-1 (STM-0/AU-3) paths or a single STS-3c (STM-1/AU-4) path.
  • Each channel maps three STS-1 (STM-0/AU-3) payloads or a single STS-3c (STM-1/AU-4) payload to system timing reference, accommodating plesiosynchronous timing offsets between the references through pointer processing.
  • The entire SONET/SDH transport and path overheads are extracted to and inserted from dedicated pins.
  • Frames to the SONET/SDH receive stream and inserts framing bytes and STS identification into the transmit stream and processes or inserts the transport overhead.
  • Interprets or generates the STS (AU) pointer bytes (H1, H2, H3), extracts or inserts the synchronous payload envelope(s) and processes or inserts the path overhead.
  • Supports Automatic Protection Switching (APS):
    • Ring control port communication of path REI and path RDI alarms.
    • Filters the APS channel (K1,K2) bytes into internal registers; inserts the APS channel into the transmit stream.
  • Provides Time Slot Interchange (TSI) function at the ADD and DROP TelecomBus Interfaces for grooming twelve STS-1 (STM-0/AU-3) paths.
  • Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from an ADD TelecomBus interface to a DROP TelecomBus interface.
  • Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes.
  • Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Low power 3.3 V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs.
  • Industrial temperature range (-40 °C to +85 °C).
  • 520-pin Super BGA package.
  • Supports clock recovery bypass for use in applications where external clock recovery is desired.
  • Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer, and intrinsic jitter criteria.

Applications

Channelized STS-3/STM-1 Interfaces for:
  • Optical Cross Connects.
  • Digital Cross Connects.
  • Router and Switch Line Cards.
  • ADM Aggregate Cards for TDM and Multi-service applications.
  • Terminal Multiplexers.
 
 
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