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PM5315 SPECTRA™ 2488
Monolithic SONET/SDH Payload Extractor/Aligner

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Version Issue Date

Product Brief

PDFSPECTRA-2488 Short Form Data Sheet [121 kB] PMC-2000326 2000-03-28 

Reference Design

Locked Document, Log In RequiredPDFSPECTRA-2488 with TBS QUAD OC-12 Line Card [782 kB] PMC-2000185 2002-08-21 
Locked Document, Log In RequiredPDFSPECTRA-2488 with TBS OC-48 Line Card Reference Design [782 kB] PMC-2000179 2002-08-21 

Data Sheet

Locked Document, Log In RequiredPDFSPECTRA-2488 Telecom Standard Product Data Sheet [2.78 MB] PMC-1990821 2001-11-26 

Application Note

Locked Document, Log In RequiredPDFKnowledge Base Items for the PM5315 SPECTRA-2488 [1.03 MB] PMC-2020319   2005-09-22 
Locked Document, Log In RequiredPDFSONET/SDH Bit Error Threshold Monitoring [192 KB] PMC-1950820 2003-10-15 
Locked Document, Log In RequiredPDFPM5315 SPECTRA 2488 Configuration Guide [357 kB] PMC-2012596 2002-11-25 

Errata

Locked Document, Log In RequiredPDFSPECTRA-2488 Errata [88 kB] PMC-2001834 2002-12-10 
Locked Document, Log In RequiredPDFSPECTRA-2488 Device Driver Errata [363 kB] PMC-2010048 2002-10-08 

Software Documentation

Locked Document, Log In RequiredPDFSPECTRA-2488 Driver Manual [876 kB] PMC-2001285 2001-11-21 

Software

Locked Document, Log In RequiredPDFPM5315 SPECTRA-2488 Device Driver [156 kB] PMC-2001664 Rel 1.0  2001-11-29 

Models

Locked Document, Log In RequiredPDFSPECTRA-2488 [42 kB] 1.05  2002-10-25 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the SPECTRA-2488 Revision B [89 KB] PMC-2001399 2001-11-20 

Features

  • Monolithic SONET/SDH Payload Extractor/Aligner for use in interface applications, operating at serial interface speeds of up to 2488 Mbit/s:
    • Single STS-48c (STM-16/AU4-16c).
    • Single STS-48 (STM-16/AU4-4c/AU4/AU3/TU3).
    • Quad STS-12c (STM-4/AU4-4c).
    • Quad STS-12 (STM-4/AU4/AU3/TU3).
  • In single STS-48/STM-16 mode, supports a duplex 16-bit 155.52 MHz differential PECL line side interface for direct connection to external clock recovery, clock synthesis and serializer-deserializer components.
  • In quad STS-12/STM-4 mode, supports four duplex 8-bit 77.76 MHz TTL compatible line side interfaces for direct connection to external clock recovery, clock synthesis and serializer-deserializer components.
  • Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section, Multiplexer Section and High Order Path overhead.
  • In single STS-48/STM-16 mode provides a 32-bit 77.76 MHz ADD and DROP TelecomBus.
  • In quad STS-12/STM-4 mode provides four 8-bit 77.76 MHz ADD and DROP TelecomBus Interfaces.
  • Maps SONET/SDH payloads to system timing, accommodating plesiochronous timing offsets between the line and system timing references, through pointer processing.
  • The entire SONET/SDH transport and path overheads are extracted to and inserted from dedicated pins.
  • Frames to the SONET/SDH receive stream and inserts framing bytes and STS identification into the transmit stream and processes or inserts the transport overhead.
  • Interprets or generates the STS (AU) pointer bytes (H1, H2, H3), extracts or inserts the synchronous payload envelope(s) and processes or inserts the path overhead.
  • Provides Time Slot Interchange (TSI) function at the ADD and DROP TelecomBus Interfaces for grooming any legal mix of SONET/SDH paths.
  • Supports Automatic Protection Switching (APS):
    • Ring control port communication of path REI and path RDI alarms.
    • Filters the APS channel (K1,K2) bytes into internal registers, and inserts the APS channel into the transmit stream.
  • Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from an ADD TelecomBus interface to a DROP TelecomBus interface.
  • Provides a standard five signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
  • Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Low power 1.8 V CMOS core logic with 3.3 V CMOS/TTL compatible digital inputs and digital outputs. PECL inputs and outputs are 3.3 V compatible.
  • Industrial temperature range (-40 °C to +85 °C).
  • 520-pin Super BGA package.

Applications

Channelized STS-48/STM-16 or 4 x STS-12/STM-4 Interfaces for:
  • Optical Cross Connects.
  • Digital Cross Connects.
  • Router and Switch Line Cards.
  • ADM Aggregate Cards for TDM and Multiservice applications.
  • Terminal Multiplexers.
 
 
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