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PM4354 COMET™ QUAD
Four Channel Combined E1/T1/J1 Transceiver/Framer

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Version Issue Date

Product Brief

PDFPM2354-KIT COMET-QUAD Evaluator Kit Short Form Data Sheet [116 KB] PMC-2010749 2001-08-30 
PDFCOMET-QUAD Short Form Data Sheet [64 kB] PMC-2000091 2001-08-03 

Reference Design

Locked Document, Log In RequiredPDFAAL1gator-8 Paper Reference Design [2.47 MB] PMC-1991089 2001-06-06 
Locked Document, Log In RequiredPDFCOMET-QUAD Evaluator Board [2.18 MB] PMC-1991237 2001-01-16 

Data Sheet

Locked Document, Log In RequiredPDFPM4354 COMET-QUAD DATASHEET [1.65 MB] PMC-1990315 2008-09-24 

Application Note

Locked Document, Log In RequiredPDFUsing the COMET Family in Low Wander Applications [165 KB] PMC-2081192 2008-09-16 
Locked Document, Log In RequiredPDFSoftware Migration from PM4354 COMET QUAD to PM4358 COMET OCTAL and PM4359 COMET TETRA [352 KB] PMC-2060046 2008-06-03 
Locked Document, Log In RequiredPDFProgramming the XLPG (Transmit Pulse Generator) Block [642 KB] PMC-2012645 2002-03-25 
Locked Document, Log In RequiredPDFHardware Differences between COMET QUAD and COMET OCTAL/TETRA [196 KB] PMC-2061913 2006-08-28 
Locked Document, Log In RequiredPDFKnowledge Base Items for the PM4354 COMET-QUAD [1.41 MB] PMC-2020313   2004-01-22 
Locked Document, Log In RequiredPDFCOMET-QUAD Programming Guide [418 kB] PMC-2000151 2002-05-01 

Errata

Locked Document, Log In RequiredPDFPM4354 COMET-QUAD Device Errata [92 KB] PMC-2010629 2008-09-22 
Locked Document, Log In RequiredPDFCOMET-QUAD Evaluator Board Errata [459 kB] PMC-2010741 2001-04-02 

Software Documentation

Locked Document, Log In RequiredPDFCOMET-QUAD Evaluator Board Software [1.28 MB] PMC-2001854 2001-08-15 
Locked Document, Log In RequiredPDFCOMET and COMET-QUAD Device Driver Manual [882 kB] PMC-2001401 2002-12-04 

Software

Locked Document, Log In RequiredPDFCOMET-QUAD Evaluator Board Software [47.30 MB] V2.0  2002-11-29 
Locked Document, Log In RequiredPDFCOMET and COMET-QUAD Device Driver [191 kB] PMC-2001456 rel 1.1  2003-02-13 

Sales Collateral

Locked Document, Log In RequiredPDFNotice of Change - Assembly Second Source of PM4354-NI at Assembler 'M' [104 KB] PMC-2042035 2004-10-25 

Models

Locked Document, Log In RequiredPDFCOMET-QUAD [32 kB] PMC-2011344 1.01  2001-06-19 

Symbols/Footprints

Locked Document, Log In RequiredPDF PM4354 COMET-QUAD 208 PBGA CAD Symbols and Footprint [167 KB] PMC-2041264 2004-08-16 

BSDL Files

Text / Binary FileBoundary Scan Description Language (BSDL) Source Code for the PM4354 COMET-QUAD Rev. C Device PMC-2001851 2001-07-16 

Symbols/Footprints

  Version Issue Date
Locked Document, Log In RequiredZipped FilePMC-2041264 PM4354 COMET-QUAD 208 PBGA CAD Symbols and Footprint [167 KB]12004-08-16

Features

  • Monolithic device that integrates four T1/E1 framers and line interfaces for shorthaul and longhaul applications.
  • Software selectable between T1/J1 and E1 operation on a per device basis.
  • Provides digitally programmable longhaul and shorthaul pulse templates and line build out.
  • Meets or exceeds T1/J1 and E1 shorthaul and longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR-12 and CTR-13.
  • Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.
  • Provides receive equalization, clock recovery and line performance monitoring.
  • Provides transmit and receive jitter attenuation.
  • Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.
  • Provides a two-frame payload slip buffer to allow independent backplane and line timing.
  • Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI T1.408 specifications.
  • Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and N x 64 Kbit/s rates as recommended in ITU-T O.151 and O.152.
  • Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Uses line rate system clock.
  • Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test.
  • Implemented in a low power 2.5/3.3 V CMOS technology.
  • Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.
  • Provides a -40 °C to +85 °C industrial temperature operating range.

RECEIVER

  • Typical signal recovery of up to -43 dB at 1024 kHz (E1) and up to -44 dB at 772 kHz (T1/J1).
  • Guaranteed minimum signal recovery of -32 dB at 1024 kHz (E1) and -36 dB at 772 kHz (T1/J1) using PIC-22 gauge cable emulation.
  • Frames to DSX/DS-1 signals in SF, and ESF formats.
  • Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent with ITU-T G.706 specifications.
  • Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. Frames in the presence of and detects the Japanese yellow alarm.
  • Tolerates more than 0.4 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170.
  • Provides programmable in-band loopback activate and deactivate code detection.
  • Provides diagnostic, line and per-DS0 payload loopbacks.
  • Extracts up to three HDLC links to an H-MVIP Bus to support the D-channel, for ISDN Primary Rate Interfaces, and the C-channels, for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal.

TRANSMITTER

  • Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements.
  • Generates E1 pulses compliant to G.703 recommendations.
  • Provides line outputs that are current limited and may be tristated for protection or in redundant applications.
  • Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI CTR 12 and CTR 13.
  • Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
  • Supports unframed mode and framing bit, CRC, or data link by-pass.
  • Allows insertion of framed or unframed in-band loopback code sequences.
  • Allows insertion of a data link in ESF mode. Optionally inserts a datalink in the E1 national use bits.
  • Inserts, from an H-MVIP bus, up to three HDLC links to support the D-channel, for ISDN Primary Rate Interfaces, and the C-channels, for V5.1/V5.2 interfaces.
  • Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the alternate ESF CRC-6 calculation for Japanese applications.
  • Supports transmission of the alarm indication signal (AIS) and the yellow alarm signal. Supports Japanese yellow alarm generation.
  • Provides ESF bit-oriented code generation.

Applications

  • Wireless Base Transceiver Station and Digital Loop Carrier (DLCs).
  • Enterprise Router.
  • DSLAM.
  • APON Optical Network Unit (ONU).
  • Integrated Access Device (IAD).
  • Voice Gateway.
  • Channel and Data Service Units (CSU/DSU).
  • Digital Private Branch Exchanges (PBX).
  • Test Equipment.
 
 
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