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PM4332 TE32™
High Density 32 Channel T1/E1/J1 Framer

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Version Issue Date

Product Brief

PDFPM4332 TE-32 High Density 32-Channel T1/E1/J1 Framer Short Form Data Sheet [438 kB] PMC-2010117 2001-08-01 

Reference Design

Locked Document, Log In RequiredPDFOCTLIU / TE-32 Evaluation Board Software User's Guide [618 kB] PMC-2021194 2002-09-11 
Locked Document, Log In RequiredPDFOCTLIU / TE-32 Evaluation Board Software [9.21 MB] 2002-09-11 
Locked Document, Log In RequiredPDFOCTLIU/TE-32 Development Kit [2.45 MB] PMC-2012268 2002-06-05 

Data Sheet

Locked Document, Log In RequiredPDFHigh Density 32 Channel T1/E1 Framer Standard Product Data Sheet [1.35 MB] PMC-2011402 2005-11-24 

Application Note

Locked Document, Log In RequiredPDFConfiguring SBI Compatible Devices [551 KB] PMC-2020180 2007-11-20 
Locked Document, Log In RequiredPDFKnowledge Base Items for the PM4332 TE-32 [293 kB] PMC-2020309   2003-10-06 
Locked Document, Log In RequiredPDFINTERFACING THE OCTLIU WITH THE TEMAP-84 OR TE-32 [505 kB] PMC-2010994 2002-02-21 

Errata

Locked Document, Log In RequiredPDFTE-32 Production Release Errata [182 kB] PMC-2020987 2003-07-02 
Locked Document, Log In RequiredPDFTE-32 Device Driver Errata [230 kB] PMC-2021853 2002-11-01 

Software Documentation

Locked Document, Log In RequiredPDFTE-32 Device Driver Manual [1.49 MB] PMC-2020127 2002-06-12 

Software

Locked Document, Log In RequiredPDFTE-32 Device Driver [215 kB] PMC-2021051 rel 1.0  2002-06-17 

White Papers

Locked Document, Log In RequiredPDFEvolving Efficient Interconnects for High Density LIUs [143 KB] PMC-2040598 2004-06-09 

Models

Locked Document, Log In RequiredPDFTE-32 [50 kB] 1.03  2002-10-24 

BSDL Files

Text / Binary FileBOUNDARY SCAN DESCRIPTION LANGUAGE (BSDL) FOR THE PM4332 TE-32 REV. [29 kB] PMC-2020999 2002-05-15 

Features

The PM4332 TE32 is a high density 32 channel T1/E1/J1 Framer.

  • Software selectable between T1/J1 and E1 operation on a per device basis.
  • Supports a wide range of framing formats:
  • DS-1 signals in SF, SLC 96 and ESF formats.
  • TTC JT-G.704 multiframe formatted J1 signals.
  • ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.
  • Line side interface:
  • Provides a 19.44 MHz SBI bus line interface for seamless connection to multiplie PM4318 devices, PMC-Sierra's Octal T1/E1/J1 line interface.
  • System side interfaces:
  • Provides a 19.44 MHz or 77.76 MHz SBI bus system interface.
  • Supports 8 Mbit/s H-MVIP interfaces for all T1 or E1 links, a separate 8 Mbit/s H-MVIP interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP interface for all T1 or E1 CCS and V5.1/V5.2 channels.
  • Provides Inband Loopback Code generation and detection.
  • Provides an HDLC interface with 128 bytes of buffering for terminating a Facility Data Link.
  • Provides HDLC transmitters to support a serial data link for an ESF facility data link or E1 Sa-bit data.
  • Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
  • Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
  • Provides per link diagnostic and line loopbacks.
  • Provide PRBS generators and detectors for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T 0.151, 0.152.
  • Feature-rich software drivers available.
  • Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
  • Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes.

VOLTAGE

  • Low power 1.8 V/3.3 V CMOS technology. All pins are 5 V tolerant.

PACKAGE

  • 324-fine pitch PBGA package (23 mm x 23 mm).
  • Supports industrial temperature range (-40 °C to 85 °C) operation.

Applications

  • High Density T1 and E1 Port Cards.
  • Integrated Access Devices.
  • Multi-Service Switches .
  • Frame Relay or ATM Wan Access.
  • Digital Cross-Connects.
  • Voice Gateways.
 
 
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