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PM4323 OCTLIU™ LT
OCTAL T1/J1/E1 Long Haul Line Interface Unit

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Version Issue Date

Product Brief

PDFPM4323 OCTLIU LT Octal T1/E1/J1 Low Latency Transport Line Interface Device Short Form Data Sheet [135 kB] PMC-2022058 2003-06-19 

Data Sheet

Locked Document, Log In RequiredPDFOctal E1/T1/J1 Low Latency Transport Line Interface Device ASSP Telecom Standard Product Data Sheet [1.07 MB] PMC-2021612 2008-04-22 

Application Note

Locked Document, Log In RequiredPDFConfiguring SBI Compatible Devices [551 KB] PMC-2020180 2007-11-20 
Locked Document, Log In RequiredPDFMigrating from the OCTLIU/OCTLIU SH to the OCTLIU LT/OCTLIU ST [264 KB] PMC-2030056 2003-12-16 
Locked Document, Log In RequiredPDFOCTLIU LT and OCTLIU ST T1/E1 Redundancy Applications [255 KB] PMC-2020591 2003-09-03 
Locked Document, Log In RequiredPDFMeeting GR-253-Core Requirements With the TEMAP 84 and OCTLIU LT [410 KB] PMC-2030110 2003-09-26 
Locked Document, Log In RequiredPDFMeeting ITU-T G.783 Requirements With the TEMAP 84 and OCTLIU or OCTLIU LT [197 KB] PMC-2030569 2003-09-26 
Locked Document, Log In RequiredPDFMeeting GR-496-Core Requirements With the TEMAP 84 and OCTLIU LT [189 KB] PMC-2021247 2003-09-26 
Locked Document, Log In RequiredPDFKnowledge Base Items for the PM4323 OCTLIU LT [254 kB] PMC-2022101   2003-06-26 

Software

Locked Document, Log In RequiredPDFPM4323 OCTLIU-LT and OCTLIU-ST Device Driver [49 kB] PMC-2030319 Rel 1.0  2003-03-25 

Models

Locked Document, Log In RequiredPDFFLOTHERM DETAILED MODEL FOR PM4323 OCTLIU-LT [90 KB] PMC-2031471   2003-09-12 

BSDL Files

Locked Document, Log In RequiredText / Binary FileBSDL file for the PM4323, OCTLIU LT and PM4325, OCTLIU ST [23 KB] 2003-10-27 

Features

  • Monolithic device integrating eight T1/J1 or E1 short haul and long haul line interface units.
  • Software switchable between T1/J1 and E1 operation on a per-device basis.
  • Meets or exceeds T1/J1 and E1 short haul and long haul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, TBR 4, TBR 12, and TBR 13. In conjunction with the TEMAP 84 (PM5366), allows Add Drop Multiplexers and Terminal Multiplexers to meet GR253, GR496, and G.783.
  • Optional encoding/decoding of B8ZS, HDB3, and AMI line codes.
  • Provides receive equalization, clock recovery, and line performance monitoring.
  • Provides transmit and receive jitter attenuation.
  • Provides digitally programmable long haul and short haul line build out.
  • Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.
  • Provides PRBS generators and detectors on each tributary for errortesting at DS1 and E1 rates as recommended in ITU-T O.151.
  • Uses line rate system clock.

SYSTEM INTERFACE

  • Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s backplane buses or a SBI/SBI TR interface for low pin count interconnection of up to 11 OCTLIU LT devices to the high-density PM5366 TEMAP 84 T1/E1 framer.

RECEIVE SECTION

  • Supports T1/E1 signal reception for distances with up to 36 dB of cable attenuation at nominal conditions using PIC 22 gauge cable emulation.
  • Supports G.772 compliant non-intrusive protected monitoring points.
  • Recovers clock and data using a digital phase locked loop for high jitter tolerance.
  • Tolerates more than 0.4 UI peak-to-peak high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170.
  • Outputs dual rail recovered line pulses, a single rail DS-1/E1 signal, or parallel data in SBI/SBI TR bus format.
  • Performs B8ZS or AMI decoding when processing a bipolar DS-1 signal and HDB3 or AMI decoding whenprocessing a bipolar E1 signal.
  • Detects line code violations (LCVs), B8ZS/HDB3 line code signatures, and four (E1), eight (T1+B8ZS), or sixteen (T1 AMI) successive zeros.
  • Provides a programmable depth FIFO buffer for jitter attenuation, rate conversion, and latency optimization in the receive path.

TRANSMIT SECTION

  • Generates DSX-1 short haul and DS-1 long haul pulses with programmable pulse shape compatible with AT&T, ANSI, and ITU requirements.
  • Generates E1 pulses compliant to G.703 recommendations.
  • Provides a digitally programmable pulse shape extending up to five transmitted bit periods for custom long haul pulse shaping applications.
  • Provides line outputs that are current limited and may be tristated for protection or use in redundant applications.
  • Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer, and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13.
  • Accepts either dual rail or single rail DS-1/E1 signals or parallel data from the SBI/SBI TR interface.
  • Performs B8ZS or AMI encoding when processing a single rail or SBI/SBI TR-sourced DS-1 signal and HDB3 or AMI encoding when processing a single rail or SBI/SBI TR-sourced E1 signal.
  • Provides a programmable depth FIFO buffer for jitter attenuation, rate conversion, and latency optimization in the transmit path.

GENERAL

  • Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
  • Provides a hardware-only (no microprocessor) mode in which configuration data is read from an SPI-compatible serial PROM. The PROM interface can be cascaded such that multiple OCTLIU LT devices can be configured simultaneously from a single PROM.
  • Supports line and system side diagnostic loopbacks.
  • Provides an IEEE 1149.1 (JTAG) compliant Test Access Port (TAP) and controller for boundary scan test.
  • Implemented in low power 3.3 V tolerant 1.8/3.3 V CMOS technology.
  • Available in a high-density 288-pin Tape-SBGA package with a -40 °C to +85 °C Industrial temperature operating range.

Applications

  • Metro Optical Access Equipment.
  • Edge Router Line Cards.
  • Multi-service ATM Switch Line Cards.
  • 3G Base Wireless Equipment.
  • Digital Private Branch Exchanges (PBX).
  • Digital Access CrossConnect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX).
  • M13 Multiplexers
 
 
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