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PM2366-KIT QuadPHY II Evaluation Kit

Documents

Version Issue Date

Reference Design

Locked Document, Log In RequiredPDFQUADPHY II SMA Evaluation Board Design [16.83 MB] PMC-2001797 1  2001-03-26 

Overview

The QuadPHY-II™ Evaluation Kit is a self-contained hardware evaluation tool designed for use in a desktop PC with an available PCI slot. The QuadPHY-II Evaluation Kit is intended to provide users with an understanding of the capabilities of the QuadPHY-II. The kit contains a QuadPHY-II Evaluation Board and a Backplane Emulator Board. The two boards may be used together to verify the operation of the QuadPHY-II with highdensity connectors and various lengths of backplane trace in the signal path. Customers may also design their own backplane emulator and interface to the Evaluation Board via SMA connectors. QUADPHY-II EVALUATION CARD The QuadPHY-II Evaluation Board is designed to demonstrate the capabilities of the QuadPHY-II device. A high-speed FPGA generates byte sequences in Double Data Rate parallel form. This data feeds the QuadPHY-II, which serializes the data into a high-speed serial bit stream. The FPGA is also receives parallel data from the QuadPHY-II, and compares the received data against the expected data. Alternatively, a high-speed BERT can be used to generate high-speed serial data. The QuadPHY-II de-serializes the data to the RX parallel outputs. The FPGA can also be used to loop back the RX parallel data to the QuadPHY-II TX parallel data input. BACKPLANE ADAPTER CARD The Backplane Emulator board provides support for simulating the conditions in which the QuadPHY-II will typically operate. The customer can assess device performance over a variety of backplane trace lengths and connectors.

Features

HARDWARE FEATURES

  • PCI form factor for installation into a desktop PC.
  • High-speed coaxial and HS-3 connector interfaces.
  • High-speed FPGA for packet data generation and checking.
  • Internal (156.25 MHz crystal) or external (up to 3.2 GHz) clock source.
  • LED status indicators for the QuadPHY-II and the FPGA
  • Emulates backplanes with trace lengths of approximately 10", 20", 30", and 60"
  • MICTOR connector logic test points for monitoring of the MDIO control interface and the local bus interface.

SOFTWARE FEATURES

The demonstration software supplied with the QuadPHY-II Evaluation Kit provides a graphical user interface with support for the following major functions:

  • Interface with the QuadPHY-II reference design board through the PCI interface.
  • Read/Write access to global QuadPHY-II and FPGA registers.
  • Tx/Rx testing on all four channels of the QuadPHY-II device through the FPGA.
  • LED status and mode indicators for the QuadPHY-II and the FPGA.
  • Automated register write operations using TCL scripts.
  • User-specified default register values located in a formatted text file.

PM2366-KIT

The QuadPHY-II Evaluation Kit contains the following material:

  • Installation CD-ROM
    • Demonstration software source code
    • Documentation
  • QuadPHY-II Evaluation Board
  • Backplane Emulator Board

NOTE:

The following items are not supplied by PMC-Sierra, and are the responsibility of the user:

  • Personal computer with available PCI slot, running Windows NT 4.0 or higher.
  • SMA cables for clock source and Backplane Emulator connectors


 
 
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