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MSP8220
MSP8220 Multi-Service Security Processor
Documents
Features
Product Overview
PMC-Sierra's MSP8220 Multi-Service Security-enabled Processor is
designed to meet the needs of networking, security appliances,
and network-attached storage applications.
The MSP8220 integrates standards-based security hardware to
accelerate internet protocol security (IPSec) and secure socket
layer (SSL) performance for security appliances, firewalls,
networking, and storage applications.
The MSP8220 is part of the MSP8200 Series of highly-integrated,
feature-rich products that incorporate the high performance,
power-efficient, MIPS 34K core. The processor provides a PCI
interface, three Ethernet ports, two USB ports, ROM, Flash, DDR,
and low-speed peripheral interfaces, all connected internally to
the MIPS 34K by a high-bandwidth multi-service bus.
Benefits
- High-performance 600 MHz MIPS 34 core enables demanding
packet processing and network applications
- Highly-integrated system-on-a-chip (SoC) solution simplifies
board design, reducing component and overall system cost
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- Hardware IPSec processing frees up the CPU for other
applications
- Optimized memory controller provides low-latency, highbandwidth
access to SDRAM (DDR2-466)
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Product Highlights
Integrated Security Subsystem
- Dedicated 2-channel DMA controller for security packet
processing
- IPSec engine:
- Supports all IPSec packet transforms and implements SSL
packet transforms
- Implements DES/3DES/AES crypto and SHA-1/MD-5 hash
algorithm support
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- Integrated queue manager for intelligent buffer management
- Random number generator
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MIPS 34K Microprocessor Core
- Multi-thread-enabled 600 MHz CPU core
- 9-stage pipeline
- 64 Kbyte Instruction and Data caches
- 32 Kbyte Data Scratchpad RAM
- Supports MIPS32 Release 2 instruction set
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- MIPS16e Code Compression
- 32-bit address paths, 64-bit data paths to caches and external
interface
- DSP intruction set extensions
- EJTAG debug and off-chip trace support
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Programmable Memory Management Unit
- 8-entry Instruction TLB (ITLB) and Data TLB (DTLB)
- 32 dual-entry Joint TLB (JTLB)
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- JTLBs are sharable under software control
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High-performance Internal Multi-service Bus (MS Bus)
Architecture
- 32 bits at 233 MHz (7.4 Gbit/s)
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- DMA engines integrated for the Ethernet MACs, USB, TDM
interface, security engine, and block copy engine
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Clock Manager and Boot Controller
- In single crystal mode, all on-chip clocks are generated from a
single 12 MHz or 36 MHz crystal
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Ethernet Interface
- Three independent 10/100/1000 Ethernet MAC controllers
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- User-selectable MII, RMII, or GMII on each MAC
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PCI
- 32 bit 2.3-compliant host interface
- 33/50 MHz
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USB 2.0 Controller and PHY
- Both host and device mode of operation
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- Supports low-speed (LS) operation (1.5 Mbit/s), full-speed (FS)
operation (12 Mbit/s) and hi-speed (HS) operation (480 Mbit/s)
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System Interrupt Controller
- Handles interrupts for on-chip peripherals and 8 external
interrupts
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- Supports up to 32 PCI message signaled interrupts (MSI)
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System Logic and Peripherals Module
- Configurable external Local Bus interface that supports data
transfers up to 25 Mbytes per second
- Glueless interface to x8 Flash memories
- Clock manager and boot controller
- Serial Peripheral Interface / Microprocessor Peripheral Interface
(SPI/MPI))
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- Two-Wire serial interface
- 28 GPIO pins
- System interface controller (internal and external interrupts)
- Two external times / clock generator
- Two universal asynchronous serial (UART) interfaces
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APPLICATIONS
- Security appliances
- Firewalls
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- Networking applications
- Storage applications
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MSP8220 Multi-Service Security Processor Product Brief [184 KB] PMC-2071490