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HPFC-5600B / HPFC-5650B DX2+
Dual Channel 2.125G Fibre Channel Controller with PCI or PCI-X Bus and T10 protection information support

Product Status

    An EOL has been issued

Documents

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Version Issue Date

Product Brief

PDFHPFC-5600 / 5650 DX2+ Product Brief [220 KB] PMC-2060405 1  2004-12-15 

Features

  • The DX2+ with EDC (Error Detection Code) is a feature that provides a robust CRC-based data protection scheme with mechanisms to initiate, extend or terminate a protection domain.
  • Dual Channel Fibre Channel operation on one chip for the lowest overall FC solution
  • Dual function industry standard 33/66 MHz PCI or 66/100/133 MHz PCI-X backplane interface with 32/64bit support
  • 1 and 2 Gb FC operation support via internal transceivers or external HSPI-compatible (High Speed Parallel Interface)transceivers(SERDES)
  • Pin for Pin with Tachyon DX2; backwards compatible to Tachyon XL2 programming interface and all TSDK revisions
  • No external SRAM required
  • FC-AL-2 compliant
  • BIOS support
  • Supports inbound frame buffers for eight 2 KByte (payload) frames
  • Full 8-bit data parity protection
  • Ability to send High Priority frames
  • Hardware support for Class 3 and Class 2 (ACK_0 and ACK_1 model)
  • Enhanced SCSI (FCP) hardware assists
  • Secondary Port Interface for control (optional)
  • Supports all FC topologies (point-to-point, loop, and fabric)
  • Multiple outbound and inbound sequence support
  • Tachyon Product Software Developer's Kit (TSDK) available
  • SAN interoperability
 
 
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